KR980006541A - Method for manufacturing capacitor of semiconductor device - Google Patents

Method for manufacturing capacitor of semiconductor device Download PDF

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Publication number
KR980006541A
KR980006541A KR1019960025786A KR19960025786A KR980006541A KR 980006541 A KR980006541 A KR 980006541A KR 1019960025786 A KR1019960025786 A KR 1019960025786A KR 19960025786 A KR19960025786 A KR 19960025786A KR 980006541 A KR980006541 A KR 980006541A
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KR
South Korea
Prior art keywords
conductive layer
film
diffusion barrier
forming
thickness
Prior art date
Application number
KR1019960025786A
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Korean (ko)
Inventor
선호정
Original Assignee
김주용
현대전자산업주식회사
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Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019960025786A priority Critical patent/KR980006541A/en
Publication of KR980006541A publication Critical patent/KR980006541A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로, 반도체소자 상부의 하부절연층을 식각하여 형성된 콘택홀에 콘택플러그를 형성하고 상기 반도체기판의 전체표면상부에 확산방지막과 제1도전층을 순차적으로 형성한 다음, 상기 확산방지막과 제1도전층을 식각하되, 저장전극마스크를 이용하여 실시함로써 확산방지막패턴과 제1도전층패턴을 형성하고 상기 확산방지막패턴과 제1도전층패턴 측벽에 제2도전층 스패이서를 형성한 다음, 상기 반도체기판의 전체표면상부에 유전체막과 상부전극인 플레이트전극을 형성하여 상기 확산방지막이 유전체막와 접촉되지않도록 저장전극을 형성함으로써 소자의 투설전류 특성을 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 수율을 향상시키면 반도체소자의 고집적화를 가능하게 하는 기술이다.A contact plug is formed in a contact hole formed by etching a lower insulating layer on a semiconductor element. A diffusion barrier film and a first conductive layer are sequentially formed on the entire surface of the semiconductor substrate. The diffusion barrier layer and the first conductive layer are etched using a storage electrode mask to form a diffusion barrier layer pattern and a first conductive layer pattern and to form the diffusion barrier layer pattern and the first conductive layer pattern on the sidewall of the first conductive layer pattern. 2 conductive layer spacer is formed on the entire surface of the semiconductor substrate and then a dielectric film and a plate electrode serving as an upper electrode are formed on the entire surface of the semiconductor substrate to form a storage electrode so that the diffusion prevention film is not in contact with the dielectric film, Thereby improving the characteristics and reliability of the semiconductor device and improving the yield of the semiconductor device. As a result, It is a technology for enabling.

Description

반도체소자의 캐패시터 제조방법Method for manufacturing capacitor of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1a도 내지 제11도는 본 발명의 실시예에 따른 반도체소자의 캐패시터 제조방법을 도시한 단면도.FIGS. 1A to 11 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention; FIGS.

Claims (11)

반도체기판 상부의 하부절연층을 식각하여 형성된 콘택홀에 콘택플러그를 형성하는 공정과, 상기 반도체 기판의 전체표면상부에 확산방지막과 제1전도층 각각 소정두께 형성하는 공정과, 상기 확산방지막과 제1전도층을 식각하되, 저장전극마스크를 이용하여 실시함으로써 확산방지막패턴과 제1도전층패턴을 형성하는 공정과, 상기 반도체기판의 전체표면상부에 제2도전층을 일정두께 형성하는 공정과, 상기 제2도전층을 이방성식각하여 상기 확산방지막패턴과 제1도전층패턴 측벽에 제2도전층 스페이서를 형성하는 공정과, 상기 반도체기관의 전체표면상부에 유전체막과 상부전극인 플레이트전극을 형성하는 공정을 포함하는 반도체소자의 캐패시터 제조방법.Forming a contact plug in a contact hole formed by etching a lower insulating layer on a semiconductor substrate; forming a diffusion barrier layer and a first conductive layer on the entire surface of the semiconductor substrate; Forming a diffusion barrier film pattern and a first conductive layer pattern by etching the conductive layer using a storage electrode mask; forming a second conductive layer on the entire surface of the semiconductor substrate to a predetermined thickness; Forming a diffusion barrier film pattern and a second conductive layer spacer on the sidewalls of the first conductive layer pattern by anisotropically etching the second conductive layer; forming a dielectric film and a plate electrode as an upper electrode on the entire surface of the semiconductor engine Wherein the step of forming the capacitor comprises the steps of: 제1항에 있어서, 상기 확산방지막은 티타늄막과 티타늄질화막의 적층구조로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the diffusion barrier layer is formed of a titanium film and a titanium nitride film. 제2항에 있어서, 상기 티타늄막은 100∼500Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 2, wherein the titanium film is formed to a thickness of about 100 to 500 ANGSTROM. 제2항에 있어서, 상기 티타늄질화막은 300∼1000Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 2, wherein the titanium nitride layer is formed to a thickness of about 300 to 1000 angstroms. 제1항에 있어서, 상기 제1전도층과 제2전도층은 플라티늄박막으로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the first conductive layer and the second conductive layer are formed of a platinum thin film. 제1항 또는 제5항에 있어서, 상기 제1도전층은 2000∼8000Å정도의 두께로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1 or 5, wherein the first conductive layer has a thickness of about 2000 to 8000 ANGSTROM. 제1항 또는 제5항에 있어서, 상기 제2도전층은 500∼3000Å정도의 두께로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1 or 5, wherein the second conductive layer is formed to a thickness of about 500 to 3000 ANGSTROM. 제1항에 있어서, 상기 유전체막은 BST 박막으로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터의 제조방법.The method according to claim 1, wherein the dielectric film is formed of a BST thin film. 제1항 또는 제7항에 있어서, 상기 유전체막은 500∼2000Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1 or claim 7, wherein the dielectric film is formed to a thickness of about 500 to 2000 ANGSTROM. 제1항에 있어서, 상기 상부전극은 플라티늄박막으로 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the upper electrode is formed of a platinum thin film. 제1항 또는 제10항에 있어서, 상기 상부전극은 500∼2000Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.11. The method according to claim 1 or 10, wherein the upper electrode is formed to a thickness of about 500 to 2000 ANGSTROM. ※ 참고사항 : 최초 출원된 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the original application.
KR1019960025786A 1996-06-29 1996-06-29 Method for manufacturing capacitor of semiconductor device KR980006541A (en)

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KR1019960025786A KR980006541A (en) 1996-06-29 1996-06-29 Method for manufacturing capacitor of semiconductor device

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KR1019960025786A KR980006541A (en) 1996-06-29 1996-06-29 Method for manufacturing capacitor of semiconductor device

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