KR980005621A - Method for manufacturing storage electrode of semiconductor device - Google Patents

Method for manufacturing storage electrode of semiconductor device Download PDF

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Publication number
KR980005621A
KR980005621A KR1019960025784A KR19960025784A KR980005621A KR 980005621 A KR980005621 A KR 980005621A KR 1019960025784 A KR1019960025784 A KR 1019960025784A KR 19960025784 A KR19960025784 A KR 19960025784A KR 980005621 A KR980005621 A KR 980005621A
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KR
South Korea
Prior art keywords
forming
etching
storage electrode
barrier layer
layer
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Application number
KR1019960025784A
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Korean (ko)
Inventor
이호석
전범진
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김주용
현대전자산업 주식회사
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Priority to KR1019960025784A priority Critical patent/KR980005621A/en
Publication of KR980005621A publication Critical patent/KR980005621A/en

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Abstract

본 발명은 반도체 소자의 저장전극 제조방법에 관한 것으로, 하부절연층이 형성된 반도체 기판 상부에 식각장벽층을 형성하고 상기 식각장벽층 상부에 희생절연막을 일정두께 형성한 다음, 상기 희생 절연막을 콘택 마스크를 이용한 식각공정으로 식각하고 상기 희생절연막 측벽에 제1 도전층 스페이서를 형성한 다음, 상기 제1 도전층 스페이서를 마스크로하여 상기 식각장벽층과 하부 절연층을 식각함으로써 콘택홀을 형성하고 상기 반도체 기판의 전체 표면 상부에 제2도전층을 일정두께 형성한 다음, 상기 제3 도전층을 식각하되, 저장전극마스크를 이용하여 상기 식각 장벽층을 노출시키고 상기 식각장벽층을 제거하여 표면적이 증가된 저장전극을 형성하되, 자기정렬 콘택공정과 저장전극 형성공정을 동시에 실시하여 공정을 단순화 시키고 표면적이 증가된 저장전극을 형성함으로써 반도체 소자의 고집적화에 충분한 정전용량을 갖는 캐패시터를 형성할 수 있어 반도체 소자의 생산성을 향상시키며 반도체 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체 소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for manufacturing a storage electrode of a semiconductor device, which comprises forming an etching barrier layer on a semiconductor substrate having a lower insulating layer formed thereon, forming a sacrificial insulating layer on the etching barrier layer to a predetermined thickness, Forming a contact hole by etching the etch barrier layer and the lower insulating layer using the first conductive layer spacer as a mask, forming a contact hole by etching the semiconductor substrate using the first conductive layer spacer as a mask, Forming a second conductive layer over the entire surface of the substrate to a predetermined thickness and then etching the third conductive layer using the storage electrode mask to expose the etch barrier layer and remove the etch barrier layer to increase the surface area By forming the storage electrode, a self-aligned contact process and a storage electrode forming process are simultaneously performed to simplify the process, By forming the increased storage electrode, it is possible to form a capacitor having a sufficient capacitance for high integration of a semiconductor device, thereby improving the productivity of the semiconductor device and improving the characteristics and reliability of the semiconductor device, Technology.

Description

반도체 소자의 저장전극 제조방법Method for manufacturing storage electrode of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체 소자의 저장전극 제조방법을 도시한 단면도.Figures 1a to 1d are cross-sectional views illustrating a method of fabricating a storage electrode of a semiconductor device according to an embodiment of the present invention.

Claims (5)

하부절연층이 형성된 반도체 기판 상부에 식각장벽층을 일정두께 형성하는 공정과, 상기 식각장벽층 상부에 희생절연막을 일정두께 형성하는 공정과, 상기 희생절연막을 콘택마스크를 이용한 식각공정으로 식각하는 공정과, 상기 희생절연막 측벽에 제1도전층 스페이서를 형성하는 공정과, 상기 제1도전층 스페이서를 마스크로하여 상기 식각장벽층과 하부 절연층을 식각함으로써 콘택홀을 형성하는 공정과, 상기 반도체 기판의 전체 표면 상부에 제2도전층을 일정두께 형성하는 공정과, 상기 제3도전층을 식각하되, 저장 전극마스크를 이용하여 상기 식각장벽층을 노출시키는 공정과, 상기 식각장벽층을 제거하여 표면적이 증가된 저장전극을 형성하는 공정을 포함하는 반도체 소자의 저장전극 제조방법.Forming a predetermined thickness of the etching barrier layer on the semiconductor substrate on which the lower insulating layer is formed; forming a predetermined thickness of the sacrificial insulating film on the etching barrier layer; etching the sacrificial insulating film by an etching process using a contact mask; Forming a first conductive layer spacer on the sidewall of the sacrificial insulating film; etching the etching barrier layer and the lower insulating layer using the first conductive layer spacer as a mask to form a contact hole; Forming a second conductive layer on the entire surface of the first conductive layer to a predetermined thickness; etching the third conductive layer, exposing the etching barrier layer using a storage electrode mask; Thereby forming the increased storage electrode. 제1항에 있어서, 상기 식각장벽층은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 저장전극 제도방법.The method of claim 1, wherein the etch barrier layer is formed of a nitride layer. 제1항에 있어서, 상기 희생절연막은 콘택 식각공정시 제거되는 것을 특징으로 하는 반도체 소자의 저장전극 제조방법.The method of claim 1, wherein the sacrificial insulating layer is removed during a contact etching process. 제1항에 있어서, 상기 제2도전층은 상기 콘택홀이 매립되지 않도록 10~500Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 저장전극 제조방법.The method of claim 1, wherein the second conductive layer is formed to a thickness of about 10-500 Å so that the contact hole is not buried. 제1항에 있어서, 상기 식각장벽층은 타층과의 식각선택비 차이를 이용한 습식 방법으로 제거하는 것을 특징으로 하는 반도체 소자의 저장전극 제조방법.The method of claim 1, wherein the etch barrier layer is removed by a wet process using etch selectivity differences with other layers. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025784A 1996-06-29 1996-06-29 Method for manufacturing storage electrode of semiconductor device KR980005621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025784A KR980005621A (en) 1996-06-29 1996-06-29 Method for manufacturing storage electrode of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019960025784A KR980005621A (en) 1996-06-29 1996-06-29 Method for manufacturing storage electrode of semiconductor device

Publications (1)

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KR980005621A true KR980005621A (en) 1998-03-30

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