KR980005635A - METHOD FOR FORMING MULTILAYER METAL WIRING OF SEMICONDUCTOR - Google Patents

Abstract

The present invention relates to a tungsten plug capable of improving the reliability of a metal wiring by eliminating the cause of a step of a metal wiring due to the formation of a monocrystalline epitaxial silicon layer in the production of a predetermined metal wiring having contact holes with different aspect ratios, It is another object of the present invention to provide a method for manufacturing a multilayered metal wiring. In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a predetermined field oxide film on a semiconductor substrate, forming a transistor including the gate electrode and the source / In the method of manufacturing a multilayer metal wiring of a semiconductor device for forming a planarization oxide film 15 on the whole, a first contact hole 16 is formed by photolithography using dry etching to expose the source / drain electrode 14 Forming a single crystal epitaxial silicon layer 17 in the first contact hole 16 and then implanting ions into the hole; forming a second contact hole 18 by photolithography using dry etching; Thereby exposing the gate electrode 13 on the field oxide film 12 and forming a metal wiring 21 composed of the barrier metal film 19, the tungsten plug 20 and the aluminum alloy film .

Description

METHOD FOR FORMING MULTILAYER METAL WIRING OF SEMICONDUCTOR

Since this is a trivial issue, I did not include the contents of the text.

FIG. 2 is a process drawing showing a method for manufacturing a multilayer metal wiring of a semiconductor device according to an embodiment of the present invention, FIG. 2 (a) is a cross-sectional view of a substrate on which transistors are formed, 2C is a cross-sectional view showing the formation structure of a second contact hole, and FIG. 2D is a cross-sectional view showing the formation structure of a barrier metal film, a tungsten plug, and a metal wiring.

Claims (6)

A method for fabricating a multilayer metal wiring of a semiconductor device in which a predetermined field oxide film is formed on a semiconductor substrate and a transistor having a gate electrode and a source / drain electrode is formed and an oxide film for planarization is formed on the entire upper surface, Dry etching the planarization insulating film to expose the source / drain electrodes to form a first contact hole; Single crystal epitaxial silicon is grown in the first contact hole by a predetermined height. Implanting an impurity; Forming a second contact hole such that a portion of the gate electrode above the field oxide layer is exposed; And forming a metal interconnection so that a contact is formed between the first contact hole and the second contact hole. 2. The semiconductor device according to claim 1, wherein the planarization oxide film is composed of one or more of a BPSG film, a TEOS film, a TEOS-O ₃ film, a PE-TEOS film and an SOG film Way. The method of claim 1, wherein the single crystal epitaxial silicon layer is formed at the same height as the electrode on the field oxide film. The method of manufacturing a multilayered metal wiring of a semiconductor device according to claim 1, wherein the single crystal epitaxial silicon layer is ion-implanted so as to have the same impurity concentration as that of the source / drain electrode during ion implantation. The method of claim 1, wherein the metal interconnection is formed by forming a barrier metal film in the first and second contact holes and on the oxide film for planarization, filling the first and second contact holes with a plug, Wherein the step of forming the multi-layer metal wiring of the semiconductor device comprises the steps of: The method according to claim 5, wherein the plug is made of tungsten. ※ Note: It is disclosed by the contents of the first application.