KR980003886A - Method for pattern formation of semiconductor device - Google Patents

Method for pattern formation of semiconductor device Download PDF

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Publication number
KR980003886A
KR980003886A KR1019960025806A KR19960025806A KR980003886A KR 980003886 A KR980003886 A KR 980003886A KR 1019960025806 A KR1019960025806 A KR 1019960025806A KR 19960025806 A KR19960025806 A KR 19960025806A KR 980003886 A KR980003886 A KR 980003886A
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KR
South Korea
Prior art keywords
pattern
conductive layer
forming
photoresist pattern
semiconductor device
Prior art date
Application number
KR1019960025806A
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Korean (ko)
Inventor
심경진
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960025806A priority Critical patent/KR980003886A/en
Publication of KR980003886A publication Critical patent/KR980003886A/en

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  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

본 발명은 반도체소자의 패턴 형성방법에 관한 것으로, 플라즈마 식각 방법으로 감광막 패턴을 마스크로 이용하고, 하부의 도전층을 식각하여 도전층 패턴을 형성할 때 플라즈마 식각 이온물질외에 불활성기체인 아르곤(Ar)이 포함된 플라즈마에 의해 상기 감광막 패턴의 표면에 전기 전도도가 증대된 층이 형성되어 음이온이 도전층으로 이동된다. 그로인하여 식각증대 물질인 양이온이 감광막 패턴에 축적된 음이온에 의해 편향되는 문제점을 극복하여 수직한 측벽을 갖는 도전층 패턴을 형성할 수가 있다.The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly, to a method of forming a pattern of a semiconductor device, which comprises forming a conductive layer pattern by using a photoresist pattern as a mask by etching a lower conductive layer, A layer having increased electrical conductivity is formed on the surface of the photoresist pattern to transfer the anion to the conductive layer. The conductive layer pattern having vertical sidewalls can be formed by overcoming the problem that the positive ions as the etching enhancing material are deflected by the anions accumulated in the photoresist pattern.

Description

반도체 소자의 패턴 형성방법Method for pattern formation of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도 내지 제3도는 종래기술로 플라즈마 식각 방법으로 감광막 패턴을 마스크로 이용하여 도전층 패턴을 형성하는 것을 도시한 단면도이다.FIGS. 1 to 3 are cross-sectional views showing a conventional method of forming a conductive layer pattern using a photoresist pattern as a mask by a plasma etching method.

Claims (4)

반도체소자 패턴 형성 방법에 있어서, 도전층 상부에 감광막 패턴을 형성하는 단계와, 플라즈마식각 이온물질외에 불활성기체인 아르곤(Ar)이 포함된 프라즈라에 의해 상기 감광막 패턴을 마스크로 이용하고 노출된 도전층을 식각하여 수직한 측벽을 갖는 도전층 패턴을 형성하는 단계로 이루어지는 반도체소자의 패턴 형성방법.A method of forming a semiconductor device pattern, comprising: forming a photoresist pattern on a conductive layer; forming a photoresist pattern on the conductive layer using a photoresist pattern using the photoresist pattern as a mask with a plasma containing argon (Ar) And forming a conductive layer pattern having vertical sidewalls by etching the layer. 제1항에 있어서, 상기 도전층은 금속층 또는 폴리실리콘층인 것을 특징으로 하는 반도체소자의 패턴 형성방법.The method according to claim 1, wherein the conductive layer is a metal layer or a polysilicon layer. 제1항에 있어서, 상기 플라즈마식각 이온물질외에 불활성기체인 아르곤(Ar)이 포함된 플라즈마에 의해 상기 감광막 패턴의 표면에는 전기 전도도가 증대된 츠이 형성되어 감광막 패턴의 표면에 있는 음이온이 하부의 도전층으로 전달되어 수직한 측벽을 갖는 도전층 패턴을 형성하는 것을 특징으로 하는 반도체소자의 패턴 형성방법.2. The plasma display panel of claim 1, wherein a plasma having argon (Ar) as an inert gas in addition to the plasma etching ion material is formed on the surface of the photoresist pattern to increase electrical conductivity, Forming a conductive layer pattern having a vertical sidewall by being transferred to the conductive layer pattern. 제1항에 있어서, 상기 불활성기체인 아르곤(Ar)을 50-200SCCM 주입하는 것을 특징으로 하는 반도체소자의 패턴 형성방법.The method according to claim 1, wherein 50-200 SCCM of argon (Ar) is injected as the inert gas. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025806A 1996-06-29 1996-06-29 Method for pattern formation of semiconductor device KR980003886A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960025806A KR980003886A (en) 1996-06-29 1996-06-29 Method for pattern formation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960025806A KR980003886A (en) 1996-06-29 1996-06-29 Method for pattern formation of semiconductor device

Publications (1)

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KR980003886A true KR980003886A (en) 1998-03-30

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KR1019960025806A KR980003886A (en) 1996-06-29 1996-06-29 Method for pattern formation of semiconductor device

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0334312A (en) * 1989-03-18 1991-02-14 Toshiba Corp Manufacture of x-ray mask and internal stress controller for thin film
JPH04124100A (en) * 1990-09-13 1992-04-24 Oki Electric Ind Co Ltd Method for forming pattern on oxide thin film
JPH05206080A (en) * 1992-01-30 1993-08-13 Fujitsu Ltd Production of semiconductor device
JPH0613357A (en) * 1992-06-25 1994-01-21 Seiko Epson Corp Method of etching of semiconductor device
JPH0669168A (en) * 1992-08-18 1994-03-11 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0334312A (en) * 1989-03-18 1991-02-14 Toshiba Corp Manufacture of x-ray mask and internal stress controller for thin film
JPH04124100A (en) * 1990-09-13 1992-04-24 Oki Electric Ind Co Ltd Method for forming pattern on oxide thin film
JPH05206080A (en) * 1992-01-30 1993-08-13 Fujitsu Ltd Production of semiconductor device
JPH0613357A (en) * 1992-06-25 1994-01-21 Seiko Epson Corp Method of etching of semiconductor device
JPH0669168A (en) * 1992-08-18 1994-03-11 Fujitsu Ltd Manufacture of semiconductor device

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