KR980006255A - Method for forming charge storage electrode of semiconductor memory device - Google Patents

Method for forming charge storage electrode of semiconductor memory device Download PDF

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Publication number
KR980006255A
KR980006255A KR1019960026469A KR19960026469A KR980006255A KR 980006255 A KR980006255 A KR 980006255A KR 1019960026469 A KR1019960026469 A KR 1019960026469A KR 19960026469 A KR19960026469 A KR 19960026469A KR 980006255 A KR980006255 A KR 980006255A
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KR
South Korea
Prior art keywords
charge storage
storage electrode
forming
memory device
interlayer insulating
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KR1019960026469A
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Korean (ko)
Inventor
최흥길
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960026469A priority Critical patent/KR980006255A/en
Publication of KR980006255A publication Critical patent/KR980006255A/en

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Abstract

본 발명은 반도체 메모리 장치 제조 방법에 있어서, 반도체 기판상의 층간절연막을 선택식각하여 전하저장전극 콘택홀과 상기 콘택홀에서 소정거리 이격된 주변 지역에 홈을 형성하는 단계; 및 상기 콘택홀과 홈을 포함하는 층간절연막 상에 전하저장전극 전도막 패턴을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 메모리 장치의 전하저장 전극형성 방법에 관한 것으로, 전하저장전극의 표면적을 증대시키고 단차를 낮추어주어, 반도체 메모리 장치의 집적도 및 제조 수율을 향상시키는 효과가 있다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: selectively etching an interlayer insulating film on a semiconductor substrate to form a groove in a charge storage electrode contact hole and a peripheral region spaced apart from the contact hole by a predetermined distance; And forming a charge storage electrode conductive film pattern on the interlayer insulating film including the contact holes and the grooves. The method of forming a charge storage electrode of a semiconductor memory device according to claim 1, So that the degree of integration and the yield of the semiconductor memory device can be improved.

Description

반도체 메모리 장치의 전하저장전극 형성방법Method for forming charge storage electrode of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제 2a도 내지 제 2d도는 본 발명의 일실시예에 따른 전화저장전극 형성 공정도2a through 2d show a process of forming a telephone storage electrode according to an embodiment of the present invention

Claims (7)

반도체 메모리 장치 제조방법에 있어서, 반도체기판상의 층간절연막을 선택식각하여 전하저장전극 콘택홀과 상기 콘택홀에서 소정거리 이격된 주변 지역에 홈을 형성하는 단계; 및 상기 콘택홀과 홈을 포함하는 층간절연막 상에 전하저장전극 전도막 패턴을 형성하는 단계를 포함하여 이루어진 반도체 메모리 장치의 전하저장 전극 형성방법A method of fabricating a semiconductor memory device, comprising: etching an interlayer insulating film on a semiconductor substrate to form a groove in a charge storage electrode contact hole and a peripheral region spaced a predetermined distance from the contact hole; And forming a charge storage electrode conductive film pattern on the interlayer insulating film including the contact hole and the groove. 제1항에 있어서, 상기 콘택홀과 홈을 형성하는 단계는 상기 층간절연막상에 상기 층간절연막과 소정의 식각선택비를 갖는 박막을 형성하는 단계; 상기 전하저장전극 콘택지격에서 소정거리 이격된 주변지역의 상기 층간절연막 상에 상기 박막 패턴을 형성하는 단계; 상기 전하저장전극 콘택지역 및 상기 박막 패턴의 상부가 오픈된 마스크 패턴을 형성하는 단계; 상기 마스크 패턴을 식각장벽으로하여 상기 소정의 식각선택비를 갖는 식각 방법으로 노출된 상기 층간절연막과 상기 박막패턴을 식각하는 단게; 및 상기 마스크 패턴을 제거하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 메모리 장치의 전하저장전극 형성 방법The method according to claim 1, wherein the forming of the contact hole and the groove includes: forming a thin film having the predetermined etch selectivity with the interlayer insulating film on the interlayer insulating film; Forming the thin film pattern on the interlayer insulating film in a peripheral region spaced apart from the charge storage electrode contact by a predetermined distance; Forming a mask pattern in which the charge storage electrode contact region and the top of the thin film pattern are open; Etching the interlayer insulating layer and the thin film pattern exposed by the etching method having the predetermined etching selectivity with the mask pattern as an etching barrier; And removing the mask pattern. The method of forming a charge storage electrode of a semiconductor memory device according to claim 1, 제2항에 있어서, 상기 박막은 폴리실리콘막인 것을 특징으로 하는 반도체 메모리 장치의 전하저장전극 형성방법A charge storage electrode forming method of a semiconductor memory device according to claim 2, wherein the thin film is a polysilicon film 제3항에 있어서, 상기 층간절연막은 산화막인 것을 특징으로 하는 반도체 메모리 장치의 전하저장전극 형성방법The charge storage electrode forming method of claim 3, wherein the interlayer insulating film is an oxide film 제4항에 있어서, 상기 폴리실콘막과 상기 층간산화막의 식각선택비는 1:8인 것을 특징으로 하는 반도체 메모리 장치의 전하저장전극 형성방법.5. The method of claim 4, wherein the etch selectivity ratio of the polysilicon film to the interlayer oxide film is 1: 8. 제1항 내지 제6항중 어느한 항에 있어서, 상기 전하저장전극 전도막 패턴은 3차원 형상의 전하저장전극인것을 특징으로 하는 반도체 메모리 장치의 전하저장전극 형성방법The method of forming a charge storage electrode of a semiconductor memory device according to any one of claims 1 to 6, wherein the charge storage electrode conductive film pattern is a three-dimensional charge storage electrode 제6항에 있어서, 상기 3차원 형상의 전하저장전극은 종래의 실린더형 전하저장전극인 것을 특징으로하는 반도체 메모리 장치의 전하저장전극 형성 방법The charge storage electrode forming method of claim 6, wherein the three-dimensional charge storage electrode is a conventional cylindrical charge storage electrode.
KR1019960026469A 1996-06-29 1996-06-29 Method for forming charge storage electrode of semiconductor memory device KR980006255A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6882161B2 (en) 2002-12-17 2005-04-19 Samsung Electro-Mechanics Co., Ltd. Method of measuring dielectric constant of PCB for RIMM

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6882161B2 (en) 2002-12-17 2005-04-19 Samsung Electro-Mechanics Co., Ltd. Method of measuring dielectric constant of PCB for RIMM

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