KR970063493A - Method of forming a contact hole in a semiconductor device - Google Patents

Method of forming a contact hole in a semiconductor device Download PDF

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Publication number
KR970063493A
KR970063493A KR1019960004415A KR19960004415A KR970063493A KR 970063493 A KR970063493 A KR 970063493A KR 1019960004415 A KR1019960004415 A KR 1019960004415A KR 19960004415 A KR19960004415 A KR 19960004415A KR 970063493 A KR970063493 A KR 970063493A
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KR
South Korea
Prior art keywords
forming
contact hole
interlayer insulating
insulating film
photoresist pattern
Prior art date
Application number
KR1019960004415A
Other languages
Korean (ko)
Inventor
김주성
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960004415A priority Critical patent/KR970063493A/en
Publication of KR970063493A publication Critical patent/KR970063493A/en

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Abstract

반도체장치의 콘택홀 형성방법이 게시되어 있다. 본 발명은 반도체기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막의 소정영역을 노출시키는 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각 마스크로하여 상기 노출된 층간절연막을 고전력 및 고압 분위기에서 이방성 식각함으로써, 상기 포토레지스트 패턴의 측벽상부 및 표면전체에 탄소를 함유하는 물질층을 형성함과 동시에 일정깊이만큼 식각된 층간절연막 패턴을 형성하는 단계; 및 상기 탄소를 함유하는 물질층을 식각 마스크로하여 상기 층간절연막 패턴을 추가로 이방성 식각함으로써, 상기 반도체기판의 소정영역을 노출시키면서 측벽의 허리부분에 단차를 갖는 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 콘택홀 형성방법을 제공한다. 본 발명에 의하면, 하부의 크기가 상부의 크기보다 더 작은 콘택홀을 형성할 수 있다. 따라서, 후속공정에서 스퍼터링 방법으로 상기 콘택홀을 덮는 금속막을 형성할 경우 금속막의 단차도포성을 크게 개선시킬 수 있다.A method for forming a contact hole in a semiconductor device is disclosed. The present invention provides a method of manufacturing a semiconductor device, comprising: forming an interlayer insulating film on a semiconductor substrate; Forming a photoresist pattern exposing a predetermined region of the interlayer insulating film; The exposed interlayer insulating film is anisotropically etched in a high-power and high-pressure atmosphere using the photoresist pattern as an etching mask to form a material layer containing carbon on the upper sidewall and the entire surface of the photoresist pattern, Forming an interlayer insulating film pattern; And forming a contact hole having a step in a waist portion of the side wall while exposing a predetermined region of the semiconductor substrate by further anisotropically etching the interlayer insulating film pattern using the carbon containing material layer as an etching mask And a contact hole is formed in the contact hole. According to the present invention, a contact hole having a size smaller than that of the upper portion can be formed. Therefore, when a metal film covering the contact hole is formed by a sputtering method in a subsequent process, the step coverage of the metal film can be greatly improved.

Description

반도체장치의 콘택홀 형성방법Method of forming a contact hole in a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도 내지 제5도는 본 발명의 콘택홀 형성방법을 설명하기 위한 단면도들이다.FIGS. 3 through 5 are cross-sectional views illustrating a method of forming a contact hole according to the present invention.

Claims (1)

반도체기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막의 소정영역을 노출시키는 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각 마스크로하여 상기 노출된 층간절연막을 고전력및 고압 분위기에서 이방성 식각함으로써, 상기 포토레지스트 패턴의 측벽상부 및 표면전체에 탄소를 함유하는 물질층을 형성과 동시에 일정깊이만큼 식각된 층간절연막 패턴을 형성하는 단계; 및 상기 탄소를 함유하는 물질층을 식각 마스크로하여 상기 층간절연막 패턴을 추가로 이방성 식각함으로써, 상기 반도체기판의 소정영역을 노출시키면서 측벽의 허리부분에 단차를 갖는 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 콘택홀 형성방법.Forming an interlayer insulating film on a semiconductor substrate; Forming a photoresist pattern exposing a predetermined region of the interlayer insulating film; The exposed interlayer insulating film is anisotropically etched in a high-power and high-pressure atmosphere using the photoresist pattern as an etching mask to form a material layer containing carbon on the upper sidewalls and the entire surface of the photoresist pattern, Forming an interlayer insulating film pattern; And forming a contact hole having a step in a waist portion of the side wall while exposing a predetermined region of the semiconductor substrate by further anisotropically etching the interlayer insulating film pattern using the carbon containing material layer as an etching mask Wherein the contact hole is formed on the semiconductor substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960004415A 1996-02-24 1996-02-24 Method of forming a contact hole in a semiconductor device KR970063493A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960004415A KR970063493A (en) 1996-02-24 1996-02-24 Method of forming a contact hole in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960004415A KR970063493A (en) 1996-02-24 1996-02-24 Method of forming a contact hole in a semiconductor device

Publications (1)

Publication Number Publication Date
KR970063493A true KR970063493A (en) 1997-09-12

Family

ID=66222000

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960004415A KR970063493A (en) 1996-02-24 1996-02-24 Method of forming a contact hole in a semiconductor device

Country Status (1)

Country Link
KR (1) KR970063493A (en)

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