KR970076289A - High-speed D-RAM access method - Google Patents

High-speed D-RAM access method Download PDF

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Publication number
KR970076289A
KR970076289A KR1019960016186A KR19960016186A KR970076289A KR 970076289 A KR970076289 A KR 970076289A KR 1019960016186 A KR1019960016186 A KR 1019960016186A KR 19960016186 A KR19960016186 A KR 19960016186A KR 970076289 A KR970076289 A KR 970076289A
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low
ras
cas
ram
signal
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KR1019960016186A
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Korean (ko)
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KR100293358B1 (en
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손명욱
채근직
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김주용
현대전자산업 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

본 발명은 D-램 엑세스 방식에 있어서, D-램 제어기에서 타이밍을 맞출 때 RAMCLK 하나만 사용하여 설계함으로 인하여, D-램에 맞는 세밀한 타이밍 제어를 하기가 힌들었으며, 이에 따라 몇개의 웨이트 클럭을 필요로 하여 결과적으로 전체 버스 사이클의 속도가 느려졌던 점을, CPUCLK과 상기 신호가 반전된 RAMCLK를 함께 사용하여, CPUCLK이 반전된 RAMCLK이 라이징할 때 (CPUCLK이 폴링할 때) 뿐만 아니라 CPUCLK이 라이징할 때에도 타이밍을 제어하여 반 클럭 단위로 타이밍을 제어하고, DSACK*를 D-램의 엑세스 타임을 고려하여 미리 발생시킴으로 인하여, 웨이트 신호를 전혀 사용하지 않고도 D-램 제어기의 리드, 라이트 타이밍과 프로세서의 타이밍을 만족하면서, 웨이드 신호를 사용할 때보다 D-램 엑세스 속도를 증가시킬 수 있다.In the D-RAM access method, since the D-RAM controller uses only one RAMCLK to design the timing, it is necessary to perform fine timing control corresponding to the D-RAM. Accordingly, several weight clocks are required And the result that the speed of the entire bus cycle is slowed is used not only when RAMCLK inverted by CPUCLK (when CPUCLK polls) but also by CPUCLK by using CPUCLK and inverted RAMCLK together The timing of the D-RAM controller is controlled in units of half clocks, and the DSACK * is generated in advance in consideration of the access time of the D-RAM, so that the read and write timings of the D- While satisfying the timing, it is possible to increase the D-RAM access speed more than when using a wade signal.

Description

고속 D-램 엑세스 방법High-speed D-RAM access method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명의 리드 타이밍도, 제4도는 보 발명의 라이트 타이밍도, 제5도는 본 발명의 리프레시 타이밍도이다.FIG. 3 is a lead timing diagram of the present invention, FIG. 4 is a write timing diagram of the present invention, and FIG. 5 is a refresh timing diagram of the present invention.

Claims (4)

D-램 엑세스 방법에 있어서, 기준 클럭과 그 클럭이 반전된 클럭을 함께 사용하여, 기준 클럭이 라이징할 때나 폴링할 때(반전된 클럭이 라이징할 때) 신호의 타이밍을 제어하여 반 클럭 단위로 타이밍을 제어하여 웨이트 신호를 전혀 사용하지 않고, 또한 D-램 엑세스 타임을 고려하여 AS*와 DS*가 액티브 된 후에 DSACK*를 RAS*와 같게 만들어 미리 발생시킴으로써, D-램을 고속으로 엑세스 함을 특징으로 하는 고속 D-램 엑세스 방법.In a D-RAM access method, a reference clock and a clock whose clock is inverted are used together to control the timing of a signal when the reference clock is rising or polling (when the inverted clock is rising) By controlling the timing to not use the weight signal at all, but also to make the DSACK * equal to RAS * after AS * and DS * are activated considering the D-RAM access time, the D-RAM is accessed at high speed Speed D-RAM access method. 제1항에 있어서, 리드 타이밍은 RAS*는 AS*가 반전된 R-CLR 신호가 액티브 되면 하이로 되어 CPUCLK의 라이징 에지에서 AS*가 로우일 때 로우로 떨어지고, 프로세서가 제공하는 어드레스 신호를 D-램이 필요로 하는 RAS*와 CAS*로 분리시켜 주는 신호인 MUX*는 RAMCLK의 라이징 에지에서 RAS*신호가 로우일 때 로우로 되고, CAS*는 CPUCLK의 라이징 에지에서 MUX*가 로우일 때 로우가 되고, DSACK*는 D-램의 엑세스 타임을 고려하여 RAS*와 같게 만들며, D-램에서는 CAS*가 로우가 된 후에 데이타가 나오고, 프로세서에는 S2의 폴링 에지에서 DSACK*가 로우이므로 S4의 폴링 에지에서 데이타를 가져오고 AS*와 DS*를 난엑티브 시키며, RAS*, CAS*, MUX*, DSACK*는 AS*, DS*가 하이가 된 후 R-CLR에 이하여 난액티브 되어 리드 타이밍을 끝내는 것을 특징으로 하는 고속 D-램 엑세스 방법.2. The method of claim 1, wherein the read timing is RAS * when the AS-inverted R-CLR signal is active and becomes low when AS * is low at the rising edge of CPUCLK, and the address signal provided by the processor is D - MUX *, the signal that separates the RAS * and CAS * required by the RAM, is low when the RAS * signal is low on the rising edge of RAMCLK and CAS * is low when the MUX * is low on the rising edge of CPUCLK DSACK * is made equal to RAS * in consideration of the access time of D-RAM. In D-RAM, data is output after CAS * becomes low and DSACK * is low in the processor's polling edge of S2. RAS *, CAS *, MUX *, and DSACK * are active and active on R-CLR after AS * and DS * are high, And terminating the timing of the high-speed D-RAM access. 제1항에 있어서, 라이트 타이밍은 프로세서는 S2에서 데이타를 내보내고, S3에서 DS*를 액티브 시킴으로써 이를 알리며, RAS*는 AS*가 반전된 R-CLR 신호가 액티브 되면 하이로 되어 CPUCLK의 라이징 에지에서 AS*가 로우일 때 로우로 떨어지고, 프로세서가 제공하는 어드레스 신호를 D-램이 필요로 하는 RAS*와 CAS*로 분리시켜 주는 신호인 MUX*는 RAMCLK의 라이징 에지에서 RAS*신호가 로우일 때 로우로 되고, CAS*는 CPUCLK의 라이징 에지에서 MUX*가 로우일 때 로우가 되고, DSACK*는 D-램의 엑세스 타임을 고려하여 RAS*신호와 같게 만들며, D-램에서는 CAS*가 액티브 된 후에 데이타가 써지고, S2에서 DSACK*가 로우이므로 AS*와 DS*는 S5에서 난액티브 되며, RAS*, CAS*, MUX*, DSACK*는 AS*, DS*가 하이가 된 후 R-CLR에 의하여 난액티브 되어 라이트 타이밍을 끝내는 것을 특징으로 하는 고속 D-램 엑세스 방법.2. The method of claim 1, wherein the write timing is such that the processor exits the data at S2 and activates DS * at S3 so that RAS * goes high when the R-CLR signal with the AS * inverted becomes active, MUX *, which is a signal that drops to low when AS * is low and isolates the processor-provided address signals to RAS * and CAS * required by D-RAM, is the rising edge of RAMCLK when the RAS * signal is low CAS * becomes low when MUX * is low at rising edge of CPUCLK, DSACK * is made equal to RAS * signal by considering access time of D-RAM, and CAS * is active in D- AS * and DS * are active in S5, and RAS *, CAS *, MUX *, and DSACK * are set to R * CLR after AS * and DS * are high, since data is written and DSACK * And the write timing of the high-speed D- How to Access. 제1항에 있어서, 리프레시 타이밍은 D-램 리프레시 시간에 맞춰 RESCLK이 하이로 되면 RFRQ*가 로우로 되고, 리프레시 기간을 알리는 RFSH*신호는 RERQ*가 로우이고 AS*가 하이일 때 RAMCLK의 라이징 에지에서 액티브 되고, RFRQ는 난액티브 되면, 리프레시 기간 동안 CPUCLK의 라이징 에지에서 CAS*는 RAS*와 반대로 변하고 RAS*는 CAS*에 같게 변하며(S2의 라이징 에지에서 RAS*는 CAS*가 하이이므로 한 클럭 뒤에까지 하이가 계속되고, CAS*는 RAS*가 하이이므로 한 클럭 뒤에까지 로우로 계속된다). RFSH* 신호는 RAMCLK의 라이징 에지에서 CAS*가 RAS*가 로우이면 계속 로우로 되고, 리프레시 기간을 벗어난 후 RAS*는 MUX*가 하이이고 AS*가 로우이면 액태브 되고, 프로세서가 제공하는 어드레스 신호를 D-램이 필요로 하는 RAS*와 CAS*로 분리시켜 주는 신호인 MUX*는 RAMCLK의 라이징 에지에서 RAS*신호가 로우일 때 로우가 되고, CAS*는 CPUCLK의 라이징 에지에서 MUX*가 로우리 때 로우가 되고, DSACK*는 D-램의 엑세스 타임을 고려하여 RAS*신호와 같게 만들며, D-램에서는 CAS*가 로우가 된 후 데이타가 나오거나 써지고, 프로세서에서는 S2의 폴링 에지에서 DSACK*가 로우이므로 S4의2. The semiconductor memory device according to claim 1, wherein the RFRQ * signal is low when RESCLK is high in response to the D-RAM refresh time, and the RFSH * signal indicating the refresh period is low when RERQ * is low and AS * When RFRQ is active at the edge, CAS * changes to RAS * at the rising edge of CPUCLK during the refresh period and RAS * changes to CAS * (RAS * at Rising edge of S2 is high because CAS * is high) High continues to the end of the clock, CAS * continues low until one clock after RAS * is high). The RFSH * signal is asserted when CAS * at Rising edge of RAMCLK goes low when RAS * is low, and after exiting the refresh period, RAS * is asserted when MUX * is high and AS * is low, Which is the signal that separates RAS * and CAS * into the RAS * and CAS * required by D-RAM, becomes low when the RAS * signal is low on the rising edge of RAMCLK and CAS * is low on the rising edge of CPUCLK. The DSACK is made equal to the RAS * signal in consideration of the access time of the D-RAM. In the D-RAM, the data is written or written after the CAS * becomes low, Because S4 is low 폴링 에지에서 데이타를 래치하고, AS*와 DS*를 난엑티브 시키며, RAS*, CAS*, MUX*, DSACK*는 AS*, DS*가 하이가 된 후 R-CLR에 의하여 난액티브 되어 리프레시 타이밍을 마침을 특징으로 하는 고속 D-램 엑세스 방법.RAS *, CAS *, MUX *, and DSACK * are active by R-CLR after AS * and DS * are high, and refresh timing Wherein the step of terminating the D-RAM access method comprises the steps of: ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960016186A 1996-05-15 1996-05-15 High speed dram access method KR100293358B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451170B1 (en) * 2000-09-20 2004-10-02 엘지전자 주식회사 Release-guard signal generation circuit for read/write for processor
KR100496787B1 (en) * 1997-08-08 2005-09-12 삼성전자주식회사 Control method for reducing access time of fast semiconductor memory device and controller

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0291896A (en) * 1988-09-27 1990-03-30 Nec Corp Mos memory circuit
JPH02158852A (en) * 1988-12-12 1990-06-19 Mitsubishi Electric Corp Memory access control circuit
JPH05189309A (en) * 1992-01-17 1993-07-30 Fujitsu Ltd Purge system for cache memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100496787B1 (en) * 1997-08-08 2005-09-12 삼성전자주식회사 Control method for reducing access time of fast semiconductor memory device and controller
KR100451170B1 (en) * 2000-09-20 2004-10-02 엘지전자 주식회사 Release-guard signal generation circuit for read/write for processor

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