KR920013137A - DRAM controller - Google Patents

DRAM controller Download PDF

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Publication number
KR920013137A
KR920013137A KR1019900022890A KR900022890A KR920013137A KR 920013137 A KR920013137 A KR 920013137A KR 1019900022890 A KR1019900022890 A KR 1019900022890A KR 900022890 A KR900022890 A KR 900022890A KR 920013137 A KR920013137 A KR 920013137A
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KR
South Korea
Prior art keywords
control signal
signal
signal generator
address
dram
Prior art date
Application number
KR1019900022890A
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Korean (ko)
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KR930004945B1 (en
Inventor
전병천
이충근
김영곤
Original Assignee
경상현
재단법인 한국전자통신연구소
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Priority to KR1019900022890A priority Critical patent/KR930004945B1/en
Publication of KR920013137A publication Critical patent/KR920013137A/en
Application granted granted Critical
Publication of KR930004945B1 publication Critical patent/KR930004945B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

내용 없음No content

Description

디램 제어기DRAM controller

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 일실시예를 나타내는 블럭도, 제2도는 본 발명의 일실시예에 따른 타이밍도.1 is a block diagram showing an embodiment of the present invention, Figure 2 is a timing diagram according to an embodiment of the present invention.

Claims (1)

행 주소와 열 주소를 수신하는 주소 멀티플렉서(3)와 상기 주소 멀티플렉서(3)에 연결되어 디램 엑세스 신호(RAMSEL)와 읽기/쓰기신호(R/W) 및 리프레서(Refresh) 요구신호(RFRQ)를 수신하여 주소 멀티 플렉서 제어신호(COLAD)와 RAS(Row Address Strobe Signal)와 CAS(Column Address Storobe Signal) 및 WE(Write Enable Sianal)를 출력하고 엑세스 완료신호(TERM)를 시 셜 로직으로 클럭에 동기시켜 발생시키는 제어신호 발생기(2)로 구성된 디램 제어기에 있어서, 상기 제어신호 발생기(2)에 연결되어 상기 제어신호 발생기(2)의 CAS신호를 수신하여 지연시킨뒤 상기 제어신호 발생기(2)에 출력시키는 CAS지연수단(6), 상기 제어신호발생기(2)에 연결되어 상기 제어신호 발생기(2)의 RAS신호를 수신하여 지연시킨뒤 상기 제어신호 발생기(2)에 출력시키는 RAS지연수단(1)을 부가하여 디램의 엑세스 시간을 최적화 하는 것을 특징으로 하는 디램 제어기.It is connected to the address multiplexer 3 and the address multiplexer 3 which receives the row address and the column address, and the DRAM access signal RAMSEL, the read / write signal R / W and the refresh request signal RFRQ. Receive and output address multiplexer control signal (COLAD), Low Address Strobe Signal (RAS), Column Address Storobe Signal (CAS) and Write Enable Sianal (WE), and clock access completion signal (TERM) to serial logic. A DRAM controller comprising a control signal generator (2) which is generated in synchronization with the control signal, wherein the DRAM is connected to the control signal generator (2) and receives and delays a CAS signal of the control signal generator (2). RAS delay means (6) for outputting to the control signal generator (2), the RAS delay means for receiving and delaying the RAS signal of the control signal generator (2) and outputting it to the control signal generator (2) (1) add DRAM access time DRAM controller, characterized in that for optimizing. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900022890A 1990-12-31 1990-12-31 Dynamic ram controller KR930004945B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022890A KR930004945B1 (en) 1990-12-31 1990-12-31 Dynamic ram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900022890A KR930004945B1 (en) 1990-12-31 1990-12-31 Dynamic ram controller

Publications (2)

Publication Number Publication Date
KR920013137A true KR920013137A (en) 1992-07-28
KR930004945B1 KR930004945B1 (en) 1993-06-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900022890A KR930004945B1 (en) 1990-12-31 1990-12-31 Dynamic ram controller

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KR (1) KR930004945B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100640577B1 (en) * 2001-03-20 2006-10-31 삼성전자주식회사 Refresh control circuit for semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100640577B1 (en) * 2001-03-20 2006-10-31 삼성전자주식회사 Refresh control circuit for semiconductor memory device

Also Published As

Publication number Publication date
KR930004945B1 (en) 1993-06-10

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