KR960025774A - Multiplex device - Google Patents

Multiplex device Download PDF

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Publication number
KR960025774A
KR960025774A KR1019940040588A KR19940040588A KR960025774A KR 960025774 A KR960025774 A KR 960025774A KR 1019940040588 A KR1019940040588 A KR 1019940040588A KR 19940040588 A KR19940040588 A KR 19940040588A KR 960025774 A KR960025774 A KR 960025774A
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KR
South Korea
Prior art keywords
signal
multiplex
request signal
refresh request
self
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Application number
KR1019940040588A
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Korean (ko)
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KR0144408B1 (en
Inventor
황용
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940040588A priority Critical patent/KR0144408B1/en
Publication of KR960025774A publication Critical patent/KR960025774A/en
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Publication of KR0144408B1 publication Critical patent/KR0144408B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

본 발명의 멀티플렉스 장치는, 디램의 리프레쉬 요청신호를 침(chip)내부에서 자체적으로 발생시켜 리프레쉬 동작을 수행함에 있어서, 불규칙하게 입력되는 메모리 리드 및 라이트 구동신호와 일정한 주기로 입력되는 셀프 리프레쉬 요청신호가상충하는 경우 두 신호가 순차적으로 진행하게 하였다.In the multiplex device of the present invention, in performing a refresh operation by generating a refresh request signal of a DRAM inside a chip, a random refresh request signal and a self refresh request signal input at regular intervals. In the case of virtual insects, the two signals proceed sequentially.

Description

멀티 플렉스 장치Multiplex device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제일실시예에 따른 멀티플렉스의 회로도.1 is a circuit diagram of a multiplex according to the first embodiment of the present invention.

Claims (5)

셀프리프레쉬 요청신호를 칩내부에서 자체적으로 발생하여 리프레쉬 동작을 수행함에 있어서, 일정한 주기의 리프레쉬 요청신호와 불규칙하게 입력되는 메모리의 리드 및 라이트 구동신호인 로우 어드레스 스트로브 신호를 입력하여 상기 두 신호의 인에이블 상태가 상충되지 않을 때 각 신호의 인에이블 상태를 출력하는 제1멀티플렉스와, 상기 셀프 리프레쉬 요청 신호와 로우 어드레스 스트로브 신호를 입력하여 상기 두 신호의 인에이블 상태가 상충될 때 상기 로우어드레스 스트로브 신호가 라이징한 후 프리차지가 완료된 순간에 리프레쉬 요청신호를 출력하는 제2멀티플렉스와, 상기제1 및 제2 멀티플렉스로 부터의 신호를 논리조합하여 상기 메모리 리드 및 라이트 모드와 셀프 리프레쉬 모드가 상충하지 않고 독립적으로 진행하게 하는 논리조합 수단을 구비한 것을 특징으로 하는 멀티플렉스 장치.In performing a refresh operation by generating a cell refresh request signal in the chip itself, the input signal of the two signals is input by inputting a refresh request signal of a certain period and a row address strobe signal that is a read and write driving signal of an irregularly input memory. A first multiplex outputting an enable state of each signal when the enable state does not conflict, and the low address strobe when the enable states of the two signals are conflicted by inputting the self refresh request signal and the low address strobe signal; After the signal rises, the second multiplex outputting the refresh request signal at the moment when the precharge is completed and the signals from the first and second multiplexes are logically combined to provide the memory read and write modes and the self refresh mode. Logic to let you proceed independently without conflict A multiplexing device comprising a summation means. 제1항에 있어서, 상기 제2멀티플렉스가 상기 셀프 리프레쉬 요청신호가 충돌된 로우 어드레스 신호가 라이징하여 프리차지가 완료되는 시간 만큼 신호를 지연하는 제1지연수단을 구비한 것을 특징으로 하는 멀티플렉스장치.2. The multiplex according to claim 1, wherein the second multiplex comprises a first delay means for delaying the signal by a time period during which the precharge is completed by rising of the row address signal collided with the self refresh request signal. Device. 제1항에 있어서, 상기 제2멀티플렉스 상기 셀프 리프레쉬 모드에서 워드라인이 온(on)되고 비트라인의 센싱이 끝날때까지의 시간만큼 신호를 지연하는 제2지연수단을 구비한 것을 특징으로 하는 멀티플렉스 장치.2. The apparatus of claim 1, further comprising: second delay means for delaying a signal by a time period until the word line is turned on and the sensing of the bit line is completed in the second multiplex self-refresh mode. Multiplex device. 제1항에 있어서, 상기 논리조합수단에 OR게이트 인 것을 특징으로 하는 멀티플렉스 장치.The multiplexing device according to claim 1, wherein the logic combining means is an OR gate. 제1항에 있어서, 상기 제2멀티플렉스로 부터의 신호를 상기 논리조합수단쪽으로 매칭하는 것을 특징으로하는 멀티플렉스 장치.2. The multiplex apparatus according to claim 1, wherein a signal from said second multiplex is matched toward said logical combining means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040588A 1994-12-31 1994-12-31 Multiplexer apparatus KR0144408B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040588A KR0144408B1 (en) 1994-12-31 1994-12-31 Multiplexer apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040588A KR0144408B1 (en) 1994-12-31 1994-12-31 Multiplexer apparatus

Publications (2)

Publication Number Publication Date
KR960025774A true KR960025774A (en) 1996-07-20
KR0144408B1 KR0144408B1 (en) 1998-08-17

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437607B1 (en) * 2001-09-14 2004-06-30 주식회사 하이닉스반도체 Refresh generation circuit of semiconductor memory device
KR100468718B1 (en) * 2001-12-07 2005-01-29 삼성전자주식회사 Refresh control circuit and Refresh control method with no external refresh command at memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437607B1 (en) * 2001-09-14 2004-06-30 주식회사 하이닉스반도체 Refresh generation circuit of semiconductor memory device
KR100468718B1 (en) * 2001-12-07 2005-01-29 삼성전자주식회사 Refresh control circuit and Refresh control method with no external refresh command at memory device

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Publication number Publication date
KR0144408B1 (en) 1998-08-17

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