KR970067715A - 모스 트랜지스터의 제조방법 - Google Patents

모스 트랜지스터의 제조방법 Download PDF

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KR970067715A
KR970067715A KR1019960008954A KR19960008954A KR970067715A KR 970067715 A KR970067715 A KR 970067715A KR 1019960008954 A KR1019960008954 A KR 1019960008954A KR 19960008954 A KR19960008954 A KR 19960008954A KR 970067715 A KR970067715 A KR 970067715A
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forming
well
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manufacturing
type impurity
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KR1019960008954A
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KR100256296B1 (ko
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김재갑
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김주용
현대전자산업 주식회사
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Priority to KR1019960008954A priority Critical patent/KR100256296B1/ko
Priority to JP9092983A priority patent/JPH1032262A/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 펀치-스루 현상을 방지하면서 낮은 접합 용량을 갖은 모스펫 트랜지스터의 제조방법을 제공하는 것을 목적으로 한다. 이러한 목적을 달성하기 위한 모스펫의 제조방법은 반도체 기판에 형성된 N-웰과 P-웰 영역에 각각 소자 분리 절연막을 형성하는 단계; N-웰의 채널부분과 P-웰의 접합 부분을 노출시키는 마스크를 형성하는 단계; 노출된 영역에 N형 불순물을 이온주입하는 단계; 마스크를 제거하고 게이트 전극을 형성하는 단계; P-웰 영역에 마스크를 형성하여, N-웰 영역에 소오스/드레인 접합을 형성하고, N-웰 영역에 마스크를 형성하여 P-웰 영역에 소오스/드레인 접합을 형성하는 단계를 포함하는 것을 특징으로 한다.

Description

모스 트랜지스터의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도늬 (가)와 (나)는 본 발명에 따라 낮은 접합 캐패시턴트를 갖는 N-웰 내의 P모스펫 트랜지스터를 제조하는 과정을 나타낸 것으로서, 제1도의 a-a'선을 따라 절단된 단면도.

Claims (7)

  1. 반도체 기판에 형성된 N-웰과 P-웰 영역에 각각 소자 분리 절연막을 형성하는 단계; P-웰의 채널부분과 N-웰의 접합 부분을 노출시키는 마스크를 형성하는 단계; 노출된 영역에 P형 불순물을 이온주입하는 단계; 마스크를 제거하고 게이트 전극을 형성하는 단계; N-웰 영역에 마스크를 형성하여, P-웰 영역에 소오스/드레인 접합을 형성하고 P-웰 영역에 마스크를 형성하여 N-웰 영역에 소오스/드레인 접합을 형성하는 단계를 포함하는 것을 특징으로 하는 모스펫의 제조방법.
  2. 제1항에 있어서, 상기 P-형 불순물은 붕소(B)인 것을 특징으로 하는 모스펫의 제조방법.
  3. 제1항에 있어서, 상기 P형 불순물은 BF2인것을 특징으로 하는 모스펫의 제조방법.
  4. 제2항 또는 제3항에 있어서, 상기 P형의 불순물의 주입량은 5E10 내지 5E12/cm2인것을 특징으로 하는 모스펫의 제조방법.
  5. 반도체 기판에 형성된 N-웰과 P-웰 영역에 각각 소자 분리 절연막을 형성하는 단계; N-웰의 채널부분과 P-웰의 접합 부분을 노출시키는 마스크를 형성하는 단계; 노출된 영역에 N형 불순물을 이온주입하는 단계; 마스크를 제거하고 게이트 전극을 형성하는 단계; P-웰 영역에 마스크를 형성하여, N-웰 영역에 소오스/드레인 접합을 형성하고, N-웰 영역에 마스크를 형성하여 P-웰 영역에 소오스/드레인 접합을 형성하는 단계를 포함하는 것을 특징으로 하는 모스펫의 제조방법.
  6. 제5항에 있어서, 상기 N형 불순물은 인(P)인 것을 특징으로 하는 모스펫의 제조방법.
  7. 제5항 또는 제6항에 있어서, 상기 N형 불순물은 5E10∼5E12/cm2범위로 이온주입하는 것을 특징으로 하는 모스펫의 제조방법.
KR1019960008954A 1996-03-28 1996-03-29 모스 트랜지스터의 제조방법 KR100256296B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019960008954A KR100256296B1 (ko) 1996-03-29 1996-03-29 모스 트랜지스터의 제조방법
JP9092983A JPH1032262A (ja) 1996-03-28 1997-03-27 Ｃｍｏｓデバイスの製造方法

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Application Number Priority Date Filing Date Title
KR1019960008954A KR100256296B1 (ko) 1996-03-29 1996-03-29 모스 트랜지스터의 제조방법

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KR970067715A true KR970067715A (ko) 1997-10-13
KR100256296B1 KR100256296B1 (ko) 2000-05-15

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Publication number Priority date Publication date Assignee Title
JP2003060199A (ja) 2001-08-10 2003-02-28 Sanyo Electric Co Ltd 半導体装置とその製造方法
KR102110569B1 (ko) 2017-11-10 2020-05-14 주식회사 성한 디앤티 시추기용 로드 클램프 장치

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KR100256296B1 (ko) 2000-05-15

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