KR970067343A - System clock synchronization method in Sync DRAM data path - Google Patents

System clock synchronization method in Sync DRAM data path Download PDF

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Publication number
KR970067343A
KR970067343A KR1019960009626A KR19960009626A KR970067343A KR 970067343 A KR970067343 A KR 970067343A KR 1019960009626 A KR1019960009626 A KR 1019960009626A KR 19960009626 A KR19960009626 A KR 19960009626A KR 970067343 A KR970067343 A KR 970067343A
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KR
South Korea
Prior art keywords
system clock
data path
dram data
cycle
period
Prior art date
Application number
KR1019960009626A
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Korean (ko)
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KR100412061B1 (en
Inventor
이승훈
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김광호
삼성전자 주식회사
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Priority to KR1019960009626A priority Critical patent/KR100412061B1/en
Publication of KR970067343A publication Critical patent/KR970067343A/en
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Publication of KR100412061B1 publication Critical patent/KR100412061B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

시스템 클럭의 변화에도 호환성을 가지며 동기하기 위한 싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법에 관한 것이다.And more particularly, to a system clock synchronization method in a synchronous DRAM data path having compatibility with a system clock change.

2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention

시스템 클럭의 변화에도 호환성을 가지며 동기하기 위한 싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법을 제공함에 있다.The present invention also provides a method of synchronizing a system clock in a synchronous DRAM data path having compatibility with a system clock change.

3. 발명의 해결방법의 요지3. The point of the solution of the invention

시스템 클럭의 변화에도 호환성을 가지며 동기하기 위한 싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법에 있어서, 상기 싱크 디램 데이타 패스 내에 지연제어수단을 가지며, 상기 지연제어수단은 규칙적인 주기를 가지는 시스템 클럭의 주기와, 그 시스템 클럭의 주기에 동기되는 상기 데이타 패스의 회로내부클럭의 주기를 다르게 제어하는 것을 요지고 한다.A method for synchronizing a system clock in a synchronous DRAM data path having compatibility with a change in a system clock, the system clock synchronizing method comprising a delay control means in the synchronous DRAM data path, And the period of the circuit internal clock of the data path synchronized with the period of the system clock are controlled differently.

4. 발명의 중요한 용도4. Important Uses of the Invention

싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법에 적합하다.It is suitable for the system clock synchronization method in Sync DRAM data path.

Description

싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법System clock synchronization method in Sync DRAM data path

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명의 기술에 따른 싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법을 보인 도면.FIG. 2 is a diagram showing a system clock synchronization method in a sync DRAM data path according to the technique of the present invention; FIG.

Claims (3)

시스템 클럭의 변화에도 호환성을 가지며 동기하기 위한 싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법에 있어서; 상기 싱크 디램 데이타 패스 내에 지연제어수단을 가지며, 상기 지연제어수단은 규칙적인 주기를 가지는 시스템 클럭의 주기와, 그 시스템 클럭의 주기에 동기되는 상기 데이타 패스의 회로내부클럭의 주기를 다르게 제어하는 것을 특징으로 하는 싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법.A method for synchronizing a system clock in a synchronous DRAM data path having compatibility with a change in a system clock, the method comprising: Wherein the delay control means controls the period of the system clock having the regular period and the period of the circuit internal clock of the data path synchronized with the period of the system clock differently from the delay control means in the sync delay data path A method for synchronizing a system clock in a sink DRAM data path. 제1항에 있어서; 상기 지연제어수단은 상기 시스템 클럭의 주기와 그 시스템 클럭의 주기에 동기되는 상기 회로내부클럭의 주기 사이의 지연시간을 각기 다르게 제어하는 것을 특징으로 하는 싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법.The method of claim 1, further comprising: Wherein the delay control means controls the delay time between the cycle of the system clock and the cycle of the internal clock synchronized with the cycle of the system clock, respectively. 제1항에 있어서; 상기 지연제어수단 상기 시스템 클럭의 주기와 그 시스템 클럭의 주기에 동기되는 상기 회로내부클럭의 주기 사이의 첫번째 지연시간을 두번째의 지연시간보다 길게 지연시키는 것을 특징으로 하는 싱크 디램 데이타 패스에서의 시스템 클럭 동기 방법.The method of claim 1, further comprising: Wherein the delay control means delays the first delay time between the cycle of the system clock and the cycle of the internal clock synchronized with the cycle of the system clock to a time longer than a second delay time, Synchronous method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960009626A 1996-03-30 1996-03-30 Method for synchronizing system clock in synchronous dram data path KR100412061B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009626A KR100412061B1 (en) 1996-03-30 1996-03-30 Method for synchronizing system clock in synchronous dram data path

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960009626A KR100412061B1 (en) 1996-03-30 1996-03-30 Method for synchronizing system clock in synchronous dram data path

Publications (2)

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KR970067343A true KR970067343A (en) 1997-10-13
KR100412061B1 KR100412061B1 (en) 2004-04-06

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KR100772842B1 (en) 2006-08-22 2007-11-02 삼성전자주식회사 Semiconductor memory device with data paths delaying function

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US5018111A (en) * 1988-12-27 1991-05-21 Intel Corporation Timing circuit for memory employing reset function
TW198135B (en) * 1990-11-20 1993-01-11 Oki Electric Ind Co Ltd
JP3523718B2 (en) * 1995-02-06 2004-04-26 株式会社ルネサステクノロジ Semiconductor device

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