KR970003066A - Compact disc playback speed switching circuit synchronized with the block sync signal - Google Patents

Compact disc playback speed switching circuit synchronized with the block sync signal Download PDF

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Publication number
KR970003066A
KR970003066A KR1019950014845A KR19950014845A KR970003066A KR 970003066 A KR970003066 A KR 970003066A KR 1019950014845 A KR1019950014845 A KR 1019950014845A KR 19950014845 A KR19950014845 A KR 19950014845A KR 970003066 A KR970003066 A KR 970003066A
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KR
South Korea
Prior art keywords
signal
speed
block
input
synchronizing
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KR1019950014845A
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Korean (ko)
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KR0146198B1 (en
Inventor
범장수
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김광호
삼성전자 주식회사
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Priority to KR1019950014845A priority Critical patent/KR0146198B1/en
Publication of KR970003066A publication Critical patent/KR970003066A/en
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Publication of KR0146198B1 publication Critical patent/KR0146198B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
    • G11B19/20—Driving; Starting; Stopping; Control thereof
    • G11B19/28—Speed controlling, regulating, or indicating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

본 발명은 블럭 동기 신호에 동기되는 컴팩트 디스크 재생 속도 절환 회로에 관한 것으로, 마이컴으로부터의 속도 절환명령 신호, 명령 래치 클럭 신호 및 시스템 리세트 신호(SYSTEM RESET)를 입력으로 받아, 입력된 신호를 해독하여 정속,배속 또는 4배속 지정 신호를 발생시켜 출력하는 명령 디코더(10)와, 상기 명령 디코더(10)로부터 출력되는 속도 지정 신호(정속, 배속, 4배속), 시스템 리세트 신호(SYSTEM RESET) 및 컴팩트 디스크의 블럭 동기 신호(BLOCK SYNC)를 입력으로받아, 입력된 속도 지정 신호를 블럭 동기 신호(BLOCK SYNC)에 동기시켜 출력하는 블럭 싱크 동기 회로(20)로 구성되었으며, 콤팩트 디스크의 재생 속도를 변환하는데 있어서, 블럭 재생 중에 발생하는 불규칙한 재생 속도 절환 시기를 블럭 시작 순간에 맞추어 줌으로써, 재생 속도 절환시 발생하는 처리 손실을 없애는 블럭 동기 신호에 동기되는 컴팩트 디스크재생 속도 절환 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compact disc reproducing speed switching circuit synchronized with a block synchronizing signal, which receives a speed switching command signal, a command latch clock signal, and a system reset signal (SYSTEM RESET) from a microcomputer and decodes the input signal. Command decoder 10 for generating and outputting a constant speed, double speed or quadruple speed designation signal, a speed designation signal output from the command decoder 10 (constant speed, double speed, quadruple speed), and a system reset signal (SYSTEM RESET) And a block sync synchronizing circuit 20 which receives the block synchronizing signal BLOCK SYNC of the compact disc as an input and outputs the input speed specifying signal in synchronization with the block synchronizing signal BLOCK SYNC, and the reproduction speed of the compact disc. In converting, by setting the irregular playback speed switching timing that occurs during block playback to the block start instant, It relates to a compact disc reproduction speed switching circuit to be synchronized with the block sync signal to eliminate the processing cost.

Description

블럭 동기 신호에 동기되는 컴팩트 디스크 재생 속도 절환 회로Compact disc playback speed switching circuit synchronized with the block sync signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 실시예에 따른 블럭 동기 신호에 동기되는 컴팩트 디스크 재생 속도 절환 회로를 적용한 블럭도이고, 제4도는 제3도에 도시된 재생 속도 절환 회로에서 블럭 싱크 동기 회로의 상세회로도이고, 제5도는 제3도에 도시된 재생 속도 절환 회로에서 속도 지정 신호의 변화를 나타낸 타이밍도이다.3 is a block diagram of a compact disc reproducing speed switching circuit synchronized with a block synchronizing signal according to an embodiment of the present invention, and FIG. 4 is a detailed circuit diagram of a block sync synchronizing circuit in the reproducing speed switching circuit shown in FIG. 5 is a timing diagram showing a change of the speed specifying signal in the reproduction speed switching circuit shown in FIG.

Claims (3)

마이컴으로부터의 속도 절환 명령 신호, 명령 래치 클럭 신호 및 시스템 리세트 신호(SYSTEM RESET)를 입력으로 받아, 입력된 신호를 해독하여 정속, 배속 또는 4배속 지정 신호를 발생시켜 출력하는 명령 디코더(10)와; 상기명령 디코더(10)로부터 출력되는 속도 지정 신호(정속, 배속, 4배속), 시스템 리세트 신호(SYSTEM RESET) 및 블럭 동기신호(BLOCK SYNC) 또는 그것의 등가 신호를 입력으로 받아, 입력된 속도 지정 신호를 블럭 동기 신호(BLOCK SYNC)에 동기시켜 출력하는 블럭 싱크 동기 회로(20)로 이루어져 있는 것을 특징으로 하는 블럭 동기 신호에 동기되는 컴팩트 디스크재생 속도 절환 회로.A command decoder 10 that receives a speed switching command signal, a command latch clock signal, and a system reset signal from the microcomputer as an input, decodes the input signal, and generates and outputs a constant speed, double speed, or quadruple speed designation signal. Wow; The speed input signal received from the command decoder 10 (constant speed, double speed, quadruple speed), the system reset signal (SYSTEM RESET) and the block synchronization signal (BLOCK SYNC) or an equivalent signal thereof is inputted to the input speed. And a block sync synchronizing circuit (20) for synchronizing and outputting a designated signal in synchronism with a block synchronizing signal (BLOCK SYNC). 제1항에 있어서, 상기한 블럭 싱크 동기 회로(20)는 시스템 리세트 신호(SYSTEM RESET)를 각각 세트(S) 또는 리세트(R) 입력으로 받고, 블럭 동기 신호(BLOCK SYNC)를 공통 클럭 입력(CK)으로 받으며, 상기한 명령 디코더(10)로부터 출력되는 속도 지정 신호(정속, 배속, 4배속)를 각각의 입력(D)으로 받아, 입력된 블럭 동기 신호(BLOCK SYNC)에 맞게 속도 지정 신호를 동기시켜 출력하는 동기 수단(DFF1∼DFF3)으로 이루어져 있는 것을 특징으로 하는 블럭 동기 신호에동기되는 컴팩트 디스크 재생 속도 절환 회로.The block sync synchronization circuit 20 of claim 1, wherein the block sync synchronization circuit 20 receives a system reset signal SYSTEM RESET as a set S or reset R input, respectively, and receives a block synchronization signal BLOCK SYNC from a common clock. It receives the input CK and receives the speed designation signal (constant speed, double speed, quadruple speed) output from the command decoder 10 as described above to the respective inputs D, and the speed corresponds to the input block synchronization signal BLOCK SYNC. A compact disc reproduction speed switching circuit synchronized with a block synchronizing signal, comprising synchronization means (DFF1 to DFF3) for synchronizing and outputting a specified signal. 제2항에 있어서, 상기한 동기 수단(DFF1∼DFF3)은 클럭 입력(CK)에 맞추어서 출력(Q)을 내보내는 기능을갖는 플립플롭 또는 래치로 이루어져 있는 것을 특징으로 하는 블럭 동기 신호에 동기되는 컴팩트 디스크 재생 속도 절환회로.The compact synchronizing with the block synchronizing signal according to claim 2, wherein the synchronizing means (DFF1 to DFF3) comprise a flip-flop or a latch having a function of outputting the output Q in accordance with the clock input CK. Disc playback speed switching circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950014845A 1995-06-05 1995-06-05 Switching circuit of cd reproducing velocity which synchronized block signal KR0146198B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950014845A KR0146198B1 (en) 1995-06-05 1995-06-05 Switching circuit of cd reproducing velocity which synchronized block signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950014845A KR0146198B1 (en) 1995-06-05 1995-06-05 Switching circuit of cd reproducing velocity which synchronized block signal

Publications (2)

Publication Number Publication Date
KR970003066A true KR970003066A (en) 1997-01-28
KR0146198B1 KR0146198B1 (en) 1998-10-15

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KR1019950014845A KR0146198B1 (en) 1995-06-05 1995-06-05 Switching circuit of cd reproducing velocity which synchronized block signal

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KR0146198B1 (en) 1998-10-15

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