KR930011634A - Feed recognition signal generation circuit - Google Patents

Feed recognition signal generation circuit Download PDF

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Publication number
KR930011634A
KR930011634A KR1019910020138A KR910020138A KR930011634A KR 930011634 A KR930011634 A KR 930011634A KR 1019910020138 A KR1019910020138 A KR 1019910020138A KR 910020138 A KR910020138 A KR 910020138A KR 930011634 A KR930011634 A KR 930011634A
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KR
South Korea
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signal
counting
composite
generating
vertical
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KR1019910020138A
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Korean (ko)
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KR0139790B1 (en
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이태성
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강진구
삼성전자 주식회사
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Priority to KR1019910020138A priority Critical patent/KR0139790B1/en
Publication of KR930011634A publication Critical patent/KR930011634A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Signal Processing For Recording (AREA)
  • Synchronizing For Television (AREA)

Abstract

NTSC 방식의 복합 영상신호를 기수 피일드와 우수 피일드로 구별하여 신호 처리하는 영상신호 시스템에 있어서 복합 영상신호로 부터 안정된 피일드 인식 신호를 발생하기 위한 회로이다.It is a circuit for generating stable feed recognition signal from composite video signal in NTSC system video signal system that divides the composite video signal into odd and even feed signals.

복합 영상신호로 부터 수평 동기신호 및 복합 동기신호를 분리하고 상기 복합 동기신호를 적분하여 수직 동기신호를 발생하며, 상기 수직 동기신호 입력 완료시부터 상기 수평 동기신호를 설정값까지 카운팅하여 카운팅 완료시마다 하나의 펄스를 발생시켜 일정 지연시킨후 상기 복합 동기신호와 비교하여 논리 상태가 같을시에 클리어 되며 상기 수직 동기신호 입력시마다 논리 상태가 반전되는 피일드 인식 신호를 발생한다.Separating the horizontal synchronizing signal and the composite synchronizing signal from the composite video signal and generating the vertical synchronizing signal by integrating the composite synchronizing signal, counting the horizontal synchronizing signal to the set value from the completion of the vertical synchronizing signal input, one at each counting completion. After generating a predetermined delay and generating a pulse of, the feedback signal is cleared when the logic state is the same as compared with the composite synchronization signal and generates a feedback recognition signal in which the logic state is inverted every time the vertical synchronization signal is input.

따라서 복합 영상신호에 포함되어 있는 노이즈등의 영향을 받지 않는 안정된 피일드 인식 신호를 발생한다.Therefore, a stable feed recognition signal is generated that is not affected by noise or the like included in the composite video signal.

Description

피일드 인식 신호 발생회로Feed recognition signal generation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 회로도1 is a circuit diagram according to the present invention

제2도는 제1도의 각 부분의 동작 파형도2 is an operational waveform diagram of each part of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10; 동기분리부20; 적분기10; A synchronization separator 20; integrator

30; 카운터40; 1/2H 지연기30; Counter 40; 1 / 2H retarder

50; 앤드게이트60; D플립플롭50; And gate 60; D flip flop

Claims (4)

복합 영상신호를 기수 피일드와 우수 피일드로 구별하여 신호 처리하는 영상신호 처리 시스템의 피일드 인식신호 발생회로에 있어서, 복합 영상신호를 입력하여 복합 영상신호에 포함되어 있는 복합 동기신호와 수평동기신호를 분리하는 동기분리부(10)와, 상기 복합 동기신호를 적분하여 수직 동기신호를 발생하는 분리기(20)와, 상기 수직 동기신호에 의해 클리어 된후 상기 수평 동기신호를 카운팅하여 256개까지 카운팅 완료시마다 카운팅 완료 신호를 발생하는 카운터(30)와, 상기 카운터(30)의 출력 카운팅 완료 신호를 1/2H 동안 지연시키는 1/2H 지연기(40)와, 상기 복합 동기신호와 상기 1/2H 지연된 카운팅 완료 신호를 논리곱하는 논리게이트(50)와, 상기 앤드게이트(50)의 출력신호에 의해 클리어되며 상기 수직 동기신호 입력시마다 논리 상태가 반전되는 피일드 인식신호를 발생하는 플립플롭(40)으로 구성하는 것을 특징으로 하는 피일드 인식 신호 발생회로.In a feed recognition signal generating circuit of a video signal processing system for discriminating a composite video signal into odd and even feeds, the composite video signal is input and the horizontal synchronization signal is included in the composite video signal. A synchronous separator 10 for separating the signal, a separator 20 for generating the vertical synchronous signal by integrating the composite synchronous signal, and counting the horizontal synchronous signal up to 256 after being cleared by the vertical synchronous signal. A counter 30 for generating a counting completion signal each time of completion, a 1 / 2H delayer 40 for delaying the output counting completion signal of the counter 30 for 1 / 2H, the composite synchronization signal and the 1 / 2H The logic gate 50 multiplies the delayed counting completion signal and the output signal of the AND gate 50, and the logic state is inverted every time the vertical synchronization signal is input. And a flip flop 40 for generating a shield recognition signal. 제1항에 있어서, 상기 카운터(30)의 카운팅 설정값이 256으로 설정하는 것을 특징으로 하는 피일드 인식 신호 발생회로.The circuit of claim 1, wherein the counting setting value of the counter (30) is set to 256. 피일드 인식 신호 발생회로에 있어서, 복합 영상신호로 부터 수평 동기신호 및 복합 동기신호를 분리하는 동기 분리 수단과, 상기 복합 동기신호를 적분하여 수직 동기신호를 발생하는 적분수단과, 상기 수직 동기신호 입력 완료시부터 상기 수평 동기신호를 설정값까지 카운팅하여 카운팅 완료시마다 하나의 펄스를 발생하는 카운팅 수단과, 상기 카운팅수단의 출력펄스를 일정 지연시킨후 상기 복합 동기신호와 비교하여 논리 상태가 같을시에 클리어 되며 상기 수직 동기신호 입력시마다 논리 상태가 반전되는 피일드 인식 신호를 발생하는 피일드 인식 수단으로 구성하는 것을 특징으로 하는 피일드 인식 신호 발생회로.A feedback recognition signal generating circuit comprising: synchronous separating means for separating a horizontal synchronizing signal and a composite synchronizing signal from a composite video signal, an integrating means for integrating the composite synchronizing signal to generate a vertical synchronizing signal, and the vertical synchronizing signal Counting means for counting the horizontal synchronizing signal to a set value from the completion of the input and generating one pulse each time the counting is completed; and when the logic state is the same as compared with the composite synchronizing signal after a delay of the output pulse of the counting means. And a feedback recognition means for generating a feedback recognition signal that is cleared and whose logic state is inverted every time the vertical synchronization signal is input. 제3항에 있어서, 상기 카운팅 수단의 카운팅 설정값이 256으로 설정하는 것을 특징으로 하는 피일드 인식 신호 발생회로.The shield recognition signal generating circuit according to claim 3, wherein the counting setting value of said counting means is set to 256. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910020138A 1991-11-13 1991-11-13 Field identification signal generating circuit KR0139790B1 (en)

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Application Number Priority Date Filing Date Title
KR1019910020138A KR0139790B1 (en) 1991-11-13 1991-11-13 Field identification signal generating circuit

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Application Number Priority Date Filing Date Title
KR1019910020138A KR0139790B1 (en) 1991-11-13 1991-11-13 Field identification signal generating circuit

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KR930011634A true KR930011634A (en) 1993-06-24
KR0139790B1 KR0139790B1 (en) 1998-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100829105B1 (en) * 2005-08-10 2008-05-16 삼성전자주식회사 Video Signal Processing Method And Video Signal Processing Apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100829105B1 (en) * 2005-08-10 2008-05-16 삼성전자주식회사 Video Signal Processing Method And Video Signal Processing Apparatus

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KR0139790B1 (en) 1998-06-15

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