KR950024501A - Vertical Sync Separation Circuit of Composite Video Signal - Google Patents
Vertical Sync Separation Circuit of Composite Video Signal Download PDFInfo
- Publication number
- KR950024501A KR950024501A KR1019940001291A KR19940001291A KR950024501A KR 950024501 A KR950024501 A KR 950024501A KR 1019940001291 A KR1019940001291 A KR 1019940001291A KR 19940001291 A KR19940001291 A KR 19940001291A KR 950024501 A KR950024501 A KR 950024501A
- Authority
- KR
- South Korea
- Prior art keywords
- pulse width
- regulator
- composite
- output
- pulse
- Prior art date
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- Synchronizing For Television (AREA)
Abstract
본 발명은 복합영상신호의 수직동기분리회로에 관한 것으로, 복합동기신호를 입력하여 복합동기신호의 하강에지 후 소정시간 지연하는 제1펄스폭조절기와 제1펄스조절기의 출력과 복합동기신호를 입력하여 소정의 펄스폭을 갖는 하이펄스를 발생하는 제2펄스폭조절기와 제2펄스폭조절기의 출력을 입력하여 소정의 펄스폭을 가지는 로우펄스를 발생하는 제3펄스폭조절기와 제3펄스폭조절기의 출력과 제1펄스폭 조절기의 출력을 논리합하는 오아게이트를 구비하여 복합동기신호로부터 지연없이 수직동기신호를 분리한다.The present invention relates to a vertical synchronous separation circuit of a composite video signal, and inputs the combined synchronous signal and the output of the first pulse width regulator and the first pulse regulator for delaying a predetermined time after the falling edge of the composite synchronous signal by inputting the composite synchronous signal. A third pulse width controller and a third pulse width controller that generate a low pulse having a predetermined pulse width by inputting the outputs of the second pulse width regulator and the second pulse width regulator to generate a high pulse having a predetermined pulse width. An OR gate is formed to logically combine the output of the first pulse width regulator and the output of the first pulse width regulator.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 의한 복합영상신호의 수직동기 분리회로를 도시한 회로도이고,2 is a circuit diagram showing a vertical synchronous separation circuit of a composite video signal according to the present invention.
제2A∼제2E도는 제2도의 회로의 각부에서의 동작신호를 도시한 파형도이다.2A to 2E are waveform diagrams showing operation signals in respective parts of the circuit of FIG.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940001291A KR950024501A (en) | 1994-01-25 | 1994-01-25 | Vertical Sync Separation Circuit of Composite Video Signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940001291A KR950024501A (en) | 1994-01-25 | 1994-01-25 | Vertical Sync Separation Circuit of Composite Video Signal |
Publications (1)
Publication Number | Publication Date |
---|---|
KR950024501A true KR950024501A (en) | 1995-08-21 |
Family
ID=66663481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940001291A KR950024501A (en) | 1994-01-25 | 1994-01-25 | Vertical Sync Separation Circuit of Composite Video Signal |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950024501A (en) |
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1994
- 1994-01-25 KR KR1019940001291A patent/KR950024501A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |