KR950015987A - Clock signal selection method and circuit - Google Patents

Abstract

The present invention relates to a clock signal selection method and a circuit thereof, wherein the clock selection signal is a first signal in selecting one of the first and second clock signals having different periods according to the clock selection signal. A delay output generation process of controlling the second clock signal when the first delay output is generated when the clock selection signal is in the second state and generating the second delay output when the clock selection signal is the second status. And outputting a logical product of the first delayed output and the second clock signal as a final output when the clock selection signal is in the first state, and outputting the second delayed output and the first clock when the clock signal is in the second state. A clock signal selection method having an output control process of outputting a logical product of a signal to a final output and a clock signal selection circuit for achieving the same are provided.

Description

Clock signal selection method and circuit

Since this is an open matter, no full text was included.

1 is a detailed circuit diagram of a clock signal selection circuit according to the present invention.

Claims (6)

In the clock signal selection for selecting and outputting any one of the first and second clock signals having different periods according to the clock selection signal, the clock signal is composed of first and second signal delay means. When the first signal delay means is controlled to the first clock signal to input the output of the second signal delay means, when the clock selection signal is in the second state, the second signal delay means controls the first clock signal. A signal delay unit configured to input an output of the first signal delay unit; When the clock selection signal is in the first state, the output of the first signal delay unit and the logical product of the second clock signal are output as a final output. When the clock signal is in the second state, the second signal delay unit is output. And an output control unit for outputting a logical product of the first clock signal as a final output. The clock signal selection circuit of claim 1, wherein the first and second clock signals are asynchronous with each other. 2. The clock signal selection circuit according to claim 1, wherein the first and second signal delay means are D flip flops. In the click signal selection for selecting and outputting any one of the first and second clock signals having different periods according to the clock selection signal, when the clock selection signal is in the first state, the second clock signal is controlled to control the first delay. An output is generated, a delay output generation process of controlling the first clock signal when the clock selection signal is in the second state and generating a second delayed output; and the first delay when the clock selection signal is in the first state. Outputting a logical product of an output and the second clock signal as a final output, and outputting a logical product of the second delayed output and the first clock signal as a final output when the clock signal is in the second state. Clock signal selection method characterized in that. The method of claim 4, wherein the first and second clock signals are asynchronous with each other. 5. The method of claim 4, wherein the first delay output is generated by delaying the second delay output by one period of the first selection signal, and the second delay output outputs the first delay output by one period of the second selection signal. Clock signal selection method characterized in that it is generated by a delay. ※ Note: The disclosure is based on the initial application.