KR950030490A - Phase adjustment circuit - Google Patents

Phase adjustment circuit Download PDF

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Publication number
KR950030490A
KR950030490A KR1019940009191A KR19940009191A KR950030490A KR 950030490 A KR950030490 A KR 950030490A KR 1019940009191 A KR1019940009191 A KR 1019940009191A KR 19940009191 A KR19940009191 A KR 19940009191A KR 950030490 A KR950030490 A KR 950030490A
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KR
South Korea
Prior art keywords
output
data
clock
input data
outputting
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Application number
KR1019940009191A
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Korean (ko)
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KR960009974B1 (en
Inventor
김효중
이석훈
강성수
Original Assignee
양승택
재단법인 한국전자통신연구소
조백제
한국전기통신공사
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Priority to KR1019940009191A priority Critical patent/KR960009974B1/en
Publication of KR950030490A publication Critical patent/KR950030490A/en
Application granted granted Critical
Publication of KR960009974B1 publication Critical patent/KR960009974B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 동기망에서의 데이타와 클럭의 위상 조정회로에 관한 것으로, 입력되는 데이타의 2배의 주파수를 갖는 클럭을 이용하여 입력데이타와 같은 속도를 가지며 서로 90도의 위상차를 갖는 4개의 클럭을 생성하는 클럭생성수단; 상기 클럭생성수단에 접속되어 입력데이타를 래치하여 출력하는 데이타 래치수단; 상기 데이타 래치수단의 출력을 이용하여 입력데이타의 천이부를 검출하는 데이타 천이 검출수단; 상기 데이타 천이 검출수단으로부터 입력데이타의 천이가 검출되지 않더라도, 이전의 상기 데이타 천이 검출수단의 출력값을 유지하도록 하여, 최종적으로 출력 데이타의 출력 클럭이 안정된 위상관계를 유지하도록 하는 출력 안정화수단; 및 상기 출력 안정화수단의 출력을 제어신호로 하여, 상기 데이타 래치수단으로 부터의 출력 데이타 중 하나를 선택하여 출력하며, 상기 출력 안정화수단의 출력을 제어신호로 하여, 상기 클럭생성수단으로 부터의 출력 중에서 하나를 선택하여 출력하는 출력 선택수단을 구비한다.The present invention relates to a phase adjusting circuit of data and clock in a synchronous network. Using the clock having twice the frequency of the input data, four clocks having the same speed as the input data and having a phase difference of 90 degrees from each other are generated. Clock generating means; Data latch means connected to said clock generation means for latching and outputting input data; Data transition detection means for detecting a transition portion of input data using the output of the data latch means; Output stabilization means for maintaining the output value of the data transition detection means beforehand, so that the output clock of the output data maintains a stable phase relationship even if no transition of input data is detected from the data transition detection means; And selecting one of the output data from the data latching means and outputting the output of the output stabilizing means as a control signal, and outputting from the clock generating means using the output of the output stabilizing means as a control signal. And an output selecting means for selecting one of the outputs.

Description

위상조정회로Phase adjustment circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 위상 조정 회로도, 제3도는 본 발명에 따른 위상 조정 회로의 타이밍도.2 is a phase adjustment circuit diagram according to the present invention, and FIG. 3 is a timing diagram of the phase adjustment circuit according to the present invention.

Claims (1)

입력되는 데이타의 2배의 주파수를 갖는 클럭을 이용하여 입력데이타와 같은 속도를 가지며 서로 90도의 위상차를 갖는 4개의 클럭을 생성하는 클럭생성수단(10); 상기 클럭생성수단(10)에 접속되어 입력데이타를 래치하여 출력하는 데이타 래치수단(11); 상기 데이타 래치수단(11)의 출력을 이용하여 입력데이타의 천이부를 검출하는 데이타 천이 검출수단(12); 상기 데이타 천이 검출수단(12)으로부터 입력데이타의 천이가 검출되지 않더라도, 이전의 상기 데이타 천이 검출수단(12)의 출력값을 유지하도록 하여, 최종적으로 출력 데이타의 출력 클럭이 안정된 위상관계를 유지하도록 하는 출력 안정화수단(13); 및 상기 출력 안정화수단(13)의 출력을 제어신호로 하여, 상기 데이타 래치수단(11)으로 부터의 출력 데이타 중 하나를 선택하여 출력하며, 상기 출력 안정화수단(13)의 출력을 제어신호로 하여, 상기 클럭생성수단(10)으로 부터의 출력 중에서 하나를 선택하여 출력하는 출력 선택수단(14)을 구비하는 것을 특징으로 하는 위상 조정회로.Clock generation means (10) for generating four clocks having the same speed as the input data and having a phase difference of 90 degrees from each other by using a clock having twice the frequency of the input data; Data latch means (11) connected to the clock generation means (10) for latching and outputting input data; Data transition detection means (12) for detecting a transition portion of the input data by using the output of the data latch means (11); Even if the transition of the input data is not detected from the data transition detecting means 12, the output value of the previous data transition detecting means 12 is maintained so that the output clock of the output data maintains a stable phase relationship. Output stabilization means 13; And selecting one of the output data from the data latching means 11 and outputting the output of the output stabilizing means 13 as a control signal, and outputting the output of the output stabilizing means 13 as a control signal. And an output selecting means (14) for selecting and outputting one of the outputs from the clock generating means (10). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940009191A 1994-04-28 1994-04-28 Phase regulating circuit KR960009974B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940009191A KR960009974B1 (en) 1994-04-28 1994-04-28 Phase regulating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940009191A KR960009974B1 (en) 1994-04-28 1994-04-28 Phase regulating circuit

Publications (2)

Publication Number Publication Date
KR950030490A true KR950030490A (en) 1995-11-24
KR960009974B1 KR960009974B1 (en) 1996-07-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940009191A KR960009974B1 (en) 1994-04-28 1994-04-28 Phase regulating circuit

Country Status (1)

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KR (1) KR960009974B1 (en)

Also Published As

Publication number Publication date
KR960009974B1 (en) 1996-07-25

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