KR970054234A - Manufacturing Method of Flash Memory Cell - Google Patents

Manufacturing Method of Flash Memory Cell Download PDF

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Publication number
KR970054234A
KR970054234A KR1019950058451A KR19950058451A KR970054234A KR 970054234 A KR970054234 A KR 970054234A KR 1019950058451 A KR1019950058451 A KR 1019950058451A KR 19950058451 A KR19950058451 A KR 19950058451A KR 970054234 A KR970054234 A KR 970054234A
Authority
KR
South Korea
Prior art keywords
polysilicon layer
memory cell
flash memory
manufacturing
tunnel oxide
Prior art date
Application number
KR1019950058451A
Other languages
Korean (ko)
Inventor
조광현
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950058451A priority Critical patent/KR970054234A/en
Publication of KR970054234A publication Critical patent/KR970054234A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Non-Volatile Memory (AREA)

Abstract

본 발명은 플래쉬 메모리 셀의 제조 방법에 관한 것으로, 제조 공정의 단계를 단순화시키기 위하여 터널산화막을 매우 얇게 형성하고 콘트롤 게이트를 질화막 및 폴리실리콘층이 적층된 구조로 형성하여 프로그램시 전자가 상기 질화막으로 주입되도록 하므로써 소자의 동작 속도 및 수율을 향상시킬 수 있도록 한 플래쉬 메모리 셀의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a flash memory cell, in order to simplify the steps of the manufacturing process, the tunnel oxide film is formed very thin and the control gate is formed in a structure in which a nitride film and a polysilicon layer are stacked so that electrons are transferred to the nitride film during programming. The present invention relates to a method of manufacturing a flash memory cell that can be implanted to improve the operation speed and yield of the device.

Description

플래쉬 메모리 셀의 제조 방법Manufacturing Method of Flash Memory Cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명에 따른 플래쉬 메모리 셀의 제조 방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method of manufacturing a flash memory cell according to the present invention.

Claims (4)

플래쉬 메모리 셀의 제조 방법에 있어서, 웰이 형성된 실리콘기판상에 터널산화막을 형성하고, 전체 상부면에 질화막 및 제1폴리실리콘층을 순차적으로 형성한 후 상기 제1폴리실리콘층에 불순물 이온을 주입하는 단계와, 상기 단계로부터 상기 제1폴리실리콘층, 질화막 및 터널산화막을 순차적으로 패터닝하여 콘트롤 게이트를 형성하는 단계와, 상기 단계로부터 상기 실리콘기판에 소오스 및 드레인 영역을 각각 형성하는 단계와, 상기 단계로부터 전체 상부면에 유전체막 및 제2폴리실리콘층을 순차적으로 형성한 후 상기 제2폴리실리콘층에 불순물 이온을 주입하는 단계와, 상기 단계로부터 상기 제2폴리실리콘층 및 유전체막을 순차적으로 패터닝하여 셀렉트 게이트를 형성하는 단계로 이루어지는 것을 특징으로 하는 플래쉬 메모리 셀의 제조 방법.In the method of manufacturing a flash memory cell, a tunnel oxide film is formed on a silicon substrate on which a well is formed, a nitride film and a first polysilicon layer are sequentially formed on the entire upper surface thereof, and then impurity ions are implanted into the first polysilicon layer. Forming a control gate by sequentially patterning the first polysilicon layer, the nitride film, and the tunnel oxide film from the step; forming a source and a drain region on the silicon substrate, respectively, Sequentially forming a dielectric film and a second polysilicon layer on the entire upper surface from the step; implanting impurity ions into the second polysilicon layer; and sequentially patterning the second polysilicon layer and the dielectric film from the step Forming a select gate to form a flash memory cell . 제1항에 있어서, 상기 터널산화막은 열 산화 공정에 의해 형성되는 것을 특징으로 하는 플래쉬 메모리 셀의 제조 방법.The method of claim 1, wherein the tunnel oxide film is formed by a thermal oxidation process. 제1 또는 제2항에 있어서, 상기 터널산화막은 30 내지 50Å의 두께로 형성되는 것을 특징으로 하는 플래쉬 메모리 셀의 제조 방법.The method of claim 1, wherein the tunnel oxide layer has a thickness of about 30 to about 50 microns. 제1항에 있어서, 상기 질화막은 300 내지 700Å의 두께로 형성되는 것을 특징으로 하는 플래쉬 메모리 셀의 제조 방법.The method of claim 1, wherein the nitride film is formed to a thickness of 300 to 700 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950058451A 1995-12-27 1995-12-27 Manufacturing Method of Flash Memory Cell KR970054234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950058451A KR970054234A (en) 1995-12-27 1995-12-27 Manufacturing Method of Flash Memory Cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950058451A KR970054234A (en) 1995-12-27 1995-12-27 Manufacturing Method of Flash Memory Cell

Publications (1)

Publication Number Publication Date
KR970054234A true KR970054234A (en) 1997-07-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950058451A KR970054234A (en) 1995-12-27 1995-12-27 Manufacturing Method of Flash Memory Cell

Country Status (1)

Country Link
KR (1) KR970054234A (en)

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