KR970054218A - High voltage transistor manufacturing method - Google Patents

High voltage transistor manufacturing method Download PDF

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Publication number
KR970054218A
KR970054218A KR1019950049771A KR19950049771A KR970054218A KR 970054218 A KR970054218 A KR 970054218A KR 1019950049771 A KR1019950049771 A KR 1019950049771A KR 19950049771 A KR19950049771 A KR 19950049771A KR 970054218 A KR970054218 A KR 970054218A
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KR
South Korea
Prior art keywords
forming
conductive
well
insulating layer
gate electrode
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KR1019950049771A
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Korean (ko)
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KR100205307B1 (en
Inventor
박은정
임민규
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문정환
Lg 반도체 주식회사
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Priority to KR1019950049771A priority Critical patent/KR100205307B1/en
Publication of KR970054218A publication Critical patent/KR970054218A/en
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Publication of KR100205307B1 publication Critical patent/KR100205307B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)

Abstract

본 발명은 고전압 트래니스터 제조방법에 관한 것으로, 플로팅 케이트를 이용한 셀프-얼라인 공정으로 면적을 감소시키고, BVdss 특성을 개선시키는데 적당한 고전압 트랜지스터 제조방법을 제공하기 위한 것이다.The present invention relates to a high voltage transistor manufacturing method, to provide a high voltage transistor manufacturing method suitable for reducing the area and improving the BVdss characteristics by a self-aligned process using a floating kit.

이를 위한 본 발명의 고전압 트랜지스터 제조방법은 제1도전형 반도체 기판에 제2도전형 제1웰과 제2웰을 형성하고, 상기 제2도전형 제1웰과 제2웰 사이에 제1도전형 웰을 형성하는 공정, 상기 제1도전형 제1웰과 제2웰 상측의 소정 부위에 제1, 제2게이트 전극을 형성하는 공정, 상기 제1, 제2게이트 전극을 포함한 전면에 제1절연막과 다결정 실리콘을 차례로 중착한 후 패턴 마스크를 이용해 사기 다결정 실리콘과 제1절연막을 선택적으로 제거하여 플로팅 게이트 전극을 형성하는 공정, 상기 플로팅 게이트 전극을 포함한 전면에 제2절연막을 중착하여 게이트 측벽을 형성하는 공정, 상기 게이트 측벽을 마스크로 이용한 제2도전형 불순물 이온주입에 이해 제2도전형 불순물 확산영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing a high voltage transistor according to the present invention, a second conductive first well and a second well are formed on a first conductive semiconductor substrate, and a first conductive type is formed between the second conductive first well and the second well. Forming a well, forming a first and a second gate electrode on a predetermined portion of the first well and the second well, and forming a first insulating film on the entire surface including the first and second gate electrodes. And forming a floating gate electrode by selectively removing the first polycrystalline silicon and the first insulating layer using a pattern mask, and then forming a gate sidewall by depositing a second insulating layer on the entire surface including the floating gate electrode. And forming a second conductive impurity diffusion region in the second conductive impurity ion implantation using the gate sidewall as a mask.

Description

고전압 트랜지스터 제조방법High voltage transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도 (a)~(d)는 본 발명의 고전압 트랜지스터 제조방법을 나타낸 공정단면도.3 (a) to 3 (d) are process cross-sectional views showing the manufacturing method of the high voltage transistor of the present invention.

Claims (2)

제1도전형 반도체 기판에 제2도전형 제1, 제2웰을 형성하고, 상기 제2도전형 제1웰과 제2웰 사이에 제1도 전형 웰을 형성하는 공정, 상기 제1도전형 제1웰과 제2웰 상측의 소정부위에 제1, 제2게이트 전극을 형성하는 공정, 상기 제1, 제2게이트 전극을 포함한 전면에 제1절연막과 다결정 실리콘 을 차례로 중착한 후 패턴 마스크를 이용해 상기 다결정 실리콘가 제1절연막을 선택적으로 제거하여 플로팅 게이트 전극을 형성하는 공정, 상기 플로팅 게이트 전극을 포함한 전면에 제2절연막을 중착하여 게이트 측벽을 형성하는 공정, 상기 게이트 측벽을 마스크로 이용한 제2도전형 불순물 이온주입에 의해 제2도전형 불순물 확산영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 고전압 트랜지스터 제조방법.Forming second conductive first and second wells on a first conductive semiconductor substrate and forming a first conductive well between the second conductive first and second wells, the first conductive type Forming a first and a second gate electrode on predetermined portions of the first well and the second well, sequentially depositing a first insulating layer and polycrystalline silicon on the entire surface including the first and second gate electrodes, and then patterning the pattern mask. Forming a floating gate electrode by selectively removing the first insulating layer by using the polycrystalline silicon, forming a gate sidewall by depositing a second insulating layer on the entire surface including the floating gate electrode, and using the gate sidewall as a mask. And forming a second conductive impurity diffusion region by conductive impurity ion implantation. 제1항에 있어서, 제1절연막은 HLD(High Temperature Low Pressure Dielectric)층을 사용함을 특징으로하는 고전압 트랜지스터 제조방법.The method of claim 1, wherein the first insulating layer uses a high temperature low pressure dielectric (HLD) layer. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR1019950049771A 1995-12-14 1995-12-14 A method of fabricating a high voltage transistor KR100205307B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950049771A KR100205307B1 (en) 1995-12-14 1995-12-14 A method of fabricating a high voltage transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950049771A KR100205307B1 (en) 1995-12-14 1995-12-14 A method of fabricating a high voltage transistor

Publications (2)

Publication Number Publication Date
KR970054218A true KR970054218A (en) 1997-07-31
KR100205307B1 KR100205307B1 (en) 1999-07-01

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100881201B1 (en) 2003-01-09 2009-02-05 삼성전자주식회사 Memory device having side gate and method of manufacturing the same
KR100935249B1 (en) * 2003-02-07 2010-01-06 매그나칩 반도체 유한회사 High Voltage Device and Method for the same

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