KR970003695A - Transistor Manufacturing Method - Google Patents
Transistor Manufacturing Method Download PDFInfo
- Publication number
- KR970003695A KR970003695A KR1019950018121A KR19950018121A KR970003695A KR 970003695 A KR970003695 A KR 970003695A KR 1019950018121 A KR1019950018121 A KR 1019950018121A KR 19950018121 A KR19950018121 A KR 19950018121A KR 970003695 A KR970003695 A KR 970003695A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating layer
- forming
- gate electrode
- electrode pattern
- silicon
- Prior art date
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Abstract
본 발명은 트랜지스터 제조방법에 관한 것으로서, 실리콘을 포함하는 물질에서 결함이 성장하는 것을 억제하는 것에 관해 개시한다. 본 발명의 트랜지스터 제조방법은 반도체기판 상에 도전막 패턴과 제1절연막 패턴으로 이루어지는 게이트전극 패턴을 형성하는 단계, 상기 게이트전극 패턴을 마스크로 하여 그 사이에 도전성불순물을 얕게 이온주입하여 제1불순물층을 형성하는 단계, 상기 게이트전극 패턴이 형성된 반도체기판 전면에 제2절연막을 캡핑하는 단계, 상기 제2절연막 캡핑 전면에 제3절연막을 형성한 다음 식각하여 상기 게이트전극 패턴의 측벽에 스페이서를 형성하는 단계 및 상기 제1불순물영역에 깊은 제2불순물영역을 형성하는 단계를 포함한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor, and discloses suppressing the growth of defects in a material comprising silicon. In the transistor manufacturing method of the present invention, forming a gate electrode pattern consisting of a conductive film pattern and a first insulating film pattern on a semiconductor substrate, and using the gate electrode pattern as a mask, a shallow ion implantation of a conductive impurity therebetween to form a first impurity. Forming a layer, capping a second insulating layer on the entire surface of the semiconductor substrate on which the gate electrode pattern is formed, forming a third insulating layer on the entire surface of the second insulating layer capping, and then etching to form spacers on sidewalls of the gate electrode pattern And forming a deep second impurity region in the first impurity region.
본 발명에 의하면, 실리콘 포함 기판내에서 기형 결함이 성장하는 것을 억제하므로서, 접촉저항을 낮게 하고 누설전류를 작게 하여 트랜지스터의 전체적인 전기적 특성을 개선시킨다.According to the present invention, growth of malformed defects in the silicon-containing substrate is suppressed, thereby lowering the contact resistance and reducing the leakage current, thereby improving the overall electrical characteristics of the transistor.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2A도 내지 제2E도는 본 발명에 의한 트랜지스터 제조방법을 단계별로 나타낸 도면들이다.2A to 2E are diagrams showing step by step methods of manufacturing a transistor according to the present invention.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018121A KR970003695A (en) | 1995-06-29 | 1995-06-29 | Transistor Manufacturing Method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018121A KR970003695A (en) | 1995-06-29 | 1995-06-29 | Transistor Manufacturing Method |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970003695A true KR970003695A (en) | 1997-01-28 |
Family
ID=66526408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950018121A KR970003695A (en) | 1995-06-29 | 1995-06-29 | Transistor Manufacturing Method |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970003695A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190141947A (en) * | 2018-06-15 | 2019-12-26 | 삼성전자주식회사 | Method for fabricating semiconductor device |
-
1995
- 1995-06-29 KR KR1019950018121A patent/KR970003695A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190141947A (en) * | 2018-06-15 | 2019-12-26 | 삼성전자주식회사 | Method for fabricating semiconductor device |
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |