KR970018730A - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistor Download PDFInfo
- Publication number
- KR970018730A KR970018730A KR1019950031095A KR19950031095A KR970018730A KR 970018730 A KR970018730 A KR 970018730A KR 1019950031095 A KR1019950031095 A KR 1019950031095A KR 19950031095 A KR19950031095 A KR 19950031095A KR 970018730 A KR970018730 A KR 970018730A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- photoresist pattern
- type
- film
- active layer
- Prior art date
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Abstract
P+ 도핑과 N+ 도핑시 동일한 온도상승효과를 얻을 수 있는 박막트랜지스터의 제조방법에 관하여 개시한다. 본 발명은 유기기판 상에 액티브층인 다결정 실리콘막을 형성하는 단계와, 상기 다결정실리콘막 상에 게이트절연막을 형성하는 단계와, 상기 게이트절연막 상에 P형 및 N형 게이트전극을 형성하는 단계와, 상기 P형 게이트전극을 덮는 제1포토레지스트 패턴을 형성하는 단계와, 상기 액티브층인 다결정실리콘막에 N+도핑영역을 형성하기 위해 N형 불순물을 상기 제1포토레지스트 패턴을 마스크로 주입하는 단계와, 상기 마스크로 사용된 제1포토레지스트 패턴을 제거하는 단계와, 상기 유기기판의 전면에 산화막을 형성하는 단계와, 상기 N형 게이트전극을 덮는 제2포토레지스트 패턴을 형성하는 단계와, 상기 액티브층에 P+ 도핑영역을 형성을 위해 P형 불순물을 주입하는 단계와, 상기 제2포토레지스트 패턴을 제거한 후 제2층간절연막을 유리기판의 전면에 형성하는 단계를 포함하는 것을 특징으로 하는 박막트랜지스터의 제조방법을 제공한다. 본 발명에 의하면, 소오스 및 드레인을 형성하기 위하여 필요한 N+, P+ 이온주입시 주입전압의 차이에도 불구하고 상승되는 온도를 일정온도로 유지하기 위하여 N+ 도핑후 산화막을 증착한후 P+ 도핑함으로써 P+ 및 N+ 이온주입시 동일한 온도상승효과를 얻을 수 있다.Disclosed is a method of manufacturing a thin film transistor which can achieve the same temperature increase effect when P + doping and N + doping. The present invention provides a method of forming a polycrystalline silicon film as an active layer on an organic substrate, forming a gate insulating film on the polysilicon film, forming P-type and N-type gate electrodes on the gate insulating film, Forming a first photoresist pattern covering the P-type gate electrode, implanting N-type impurities into the mask to form an N + doped region in the polysilicon film as the active layer; Removing the first photoresist pattern used as the mask, forming an oxide film on the entire surface of the organic substrate, forming a second photoresist pattern covering the N-type gate electrode, and forming the active layer. Implanting a P-type impurity to form a P + doped region in the layer, and removing the second photoresist pattern; It provides a method for manufacturing a thin film transistor comprising the step of forming in. According to the present invention, in order to maintain the elevated temperature at a constant temperature despite the difference in the implantation voltage during N + and P + ion implantation necessary to form a source and a drain, P + and N + are formed by depositing P + and then doping an oxide film after N + doping. When ion implantation, the same temperature rise effect can be obtained.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도 내지 제5도는 본 발명에 의한 박막트랜지스터의 제조방법을 설명하기 위한 단면도들이다.1 to 5 are cross-sectional views illustrating a method of manufacturing a thin film transistor according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031095A KR970018730A (en) | 1995-09-21 | 1995-09-21 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031095A KR970018730A (en) | 1995-09-21 | 1995-09-21 | Method of manufacturing thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970018730A true KR970018730A (en) | 1997-04-30 |
Family
ID=66615464
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950031095A KR970018730A (en) | 1995-09-21 | 1995-09-21 | Method of manufacturing thin film transistor |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970018730A (en) |
-
1995
- 1995-09-21 KR KR1019950031095A patent/KR970018730A/en not_active Application Discontinuation
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