KR970053657A - Semiconductor chip package in which semiconductor chips are supported by bonding wires - Google Patents

Semiconductor chip package in which semiconductor chips are supported by bonding wires Download PDF

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Publication number
KR970053657A
KR970053657A KR1019950049660A KR19950049660A KR970053657A KR 970053657 A KR970053657 A KR 970053657A KR 1019950049660 A KR1019950049660 A KR 1019950049660A KR 19950049660 A KR19950049660 A KR 19950049660A KR 970053657 A KR970053657 A KR 970053657A
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KR
South Korea
Prior art keywords
semiconductor chip
package
inner lead
package body
tie bar
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KR1019950049660A
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Korean (ko)
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KR0163306B1 (en
Inventor
송영희
김강수
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김광호
삼성전자 주식회사
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Priority to KR1019950049660A priority Critical patent/KR0163306B1/en
Priority to JP8333674A priority patent/JPH09181225A/en
Publication of KR970053657A publication Critical patent/KR970053657A/en
Application granted granted Critical
Publication of KR0163306B1 publication Critical patent/KR0163306B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

본 발명은 반도체 칩 패키지에서 다이 패드, 반도체 칩, 몰딩 수지 등의 이종 물질간의 접촉 계면에서 열 팽창 계수의 차이 등 물리적인 성질의 차이에 의해 발생하는 신뢰성 저하 문제를 해결한 초박형 패키지를 제공하기 위한 것으로서, 표면에 복수개의 본딩 패드가 형성되어 있는 반도체 칩과, 상기 반도체 칩과 전기적으로 연결되는 내부 리드, 상기 내부 리드와 일체형으로 형성되어 있는 외부 리드 및 더미 타이 바를 구비하는 리드 프레임과, 상기 반도체 칩과, 본딩 와이어 및 상기 리드 프레임의 내부 리드와 더미 타이 바를 봉지하는 패키지 몸체를 구비하는 패키지로서, 상기 더미 타이 바는 상기 반도체 칩의 옆면과 실질적으로 접촉하여 상기 패키지 몸체를 형성할 때 상기 반도체 칩을 지지하는 것을 특징으로 하는 패키지가 개시되어 있다.The present invention is to provide an ultra-thin package that solves the problem of deterioration of reliability caused by the difference in physical properties such as the difference in thermal expansion coefficient at the contact interface between different materials such as die pad, semiconductor chip, molding resin in the semiconductor chip package A semiconductor device comprising: a semiconductor chip having a plurality of bonding pads formed on a surface thereof, an inner lead electrically connected to the semiconductor chip, an outer lead formed integrally with the inner lead, and a dummy tie bar; A package having a chip and a package body for enclosing a bonding wire and an inner lead of the lead frame and a dummy tie bar, wherein the dummy tie bar is in contact with a side surface of the semiconductor chip to form the package body. A package is disclosed that supports a chip.

Description

본딩 와이어에 의해 반도체 칩이 지지되는 반도체 칩 패키지Semiconductor chip package in which semiconductor chips are supported by bonding wires

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 LOC 구조를 갖는 초박형 패키지의 단면도.3 is a cross-sectional view of an ultra-thin package having a LOC structure according to the present invention.

제4도는 본 발명에 따른 패키지를 제조하는 데에 적합한 와이어 본딩 장치의 구조도.4 is a structural diagram of a wire bonding apparatus suitable for producing a package according to the present invention.

Claims (8)

A) 표면에 복수개의 본딩 패드가 형성되어 있는 반도체 칩과, B) 상기 반도체 칩과 전기적으로 연결되는 내부 리드, 상기 내부 리드와 일체형으로 형성되어 있는 외부 리드 및 더미 타이 바를 구비하는 리드 프레임과, C) 상기 반도체 칩과, 본딩 와이어 및 상기 리드 프레임의 내부 리드와 더미 타이 바를 봉지하는 패키지 몸체를 구비하는 패키지로서, 상기 더미 타이 바는 상기 반도체 칩의 옆면과 실질적으로 접촉하여 상기 패키지 몸체를 형성할 때 상기 반도체 칩을 지지하는 것을 특징으로 하는 패키지.A) a semiconductor chip having a plurality of bonding pads formed on its surface, B) a lead frame having an inner lead electrically connected to the semiconductor chip, an outer lead and a dummy tie bar integrally formed with the inner lead; C) a package having the semiconductor chip, a bonding wire, and a package body enclosing an inner lead and a dummy tie bar of the lead frame, wherein the dummy tie bar is substantially in contact with a side surface of the semiconductor chip to form the package body. When the package is characterized in that for supporting the semiconductor chip. 제1항에 있어서, 상기 복수개의 본딩 패드는 상기 반도체 칩의 표면 가장자리에 배열되어 있으며 상기 반도체 칩과 내부 리드는 본딩 와이어에 의해 전기적으로 연결되어 있는 것을 특징으로 하는 패키지.The package of claim 1, wherein the plurality of bonding pads are arranged at a surface edge of the semiconductor chip, and the semiconductor chip and the inner lead are electrically connected by bonding wires. 제2항에 있어서, 상기 패키지 몸체는 몰딩 게이트로 몰딩 컴파운드를 주입하는 트랜스퍼 몰딩 공정에 의해 형성되고, 상기 몰딩 게이트는 상부 게이트이며, 상기 반도체 칩의 밑면은 상기 패키지 몸체의 밑면과 일치하는 것을 특징으로 하는 패키지.The package body of claim 2, wherein the package body is formed by a transfer molding process of injecting a molding compound into a molding gate, the molding gate is an upper gate, and a bottom surface of the semiconductor chip coincides with a bottom surface of the package body. Package. 제1항에 있어서, 상기 복수개의 본딩 패드는 상기 반도체 칩의 표면 중앙부분에 배열되어 있으며, 상기 리드 프레임의 내부 리드는 상기 반도체 칩의 표면 위로 올라와 있는 것을 특징으로 하는 패키지.The package according to claim 1, wherein the plurality of bonding pads are arranged at the center portion of the surface of the semiconductor chip, and the inner lead of the lead frame is raised above the surface of the semiconductor chip. 제4항에 있어서, 상기 패키지 몸체는 몰딩 게이트로 몰딩 컴파운드를 주입하는 트랜스퍼 몰딩 공정에 의해 형성되고, 상기 몰딩 게이트는 하부 게이트인 것을 특징으로 하는 패키지.The package of claim 4, wherein the package body is formed by a transfer molding process of injecting molding compound into a molding gate, and the molding gate is a lower gate. 제4항에 있어서, 상기 반도체 칩의 표면은 폴리이미드로 코팅되어 있는 것을 특징으로 하는 패키지.The package according to claim 4, wherein the surface of the semiconductor chip is coated with polyimide. 제4항에 있어서, 상기 반도체 칩의 표면 위로 올라와 있는 내부 리드의 상기 반도체 칩의 표면을 향한 면에는 폴리이미드가 코팅되어 있는 것을 특징으로 하는 패키지.5. The package according to claim 4, wherein a surface of the inner lead which rises above the surface of the semiconductor chip facing the surface of the semiconductor chip is coated with polyimide. 제4항 또는 제5항에 있어서, 상기 반도체 칩의 밑면은 상기 패키지 몸체의 밑면과 일치하는 것을 특징으로 하는 패키지.The package according to claim 4 or 5, wherein a bottom surface of the semiconductor chip coincides with a bottom surface of the package body. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950049660A 1995-12-14 1995-12-14 Semiconductor chip package for support of semiconductor chip by bonding wire KR0163306B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950049660A KR0163306B1 (en) 1995-12-14 1995-12-14 Semiconductor chip package for support of semiconductor chip by bonding wire
JP8333674A JPH09181225A (en) 1995-12-14 1996-12-13 Semiconductor chip package and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950049660A KR0163306B1 (en) 1995-12-14 1995-12-14 Semiconductor chip package for support of semiconductor chip by bonding wire

Publications (2)

Publication Number Publication Date
KR970053657A true KR970053657A (en) 1997-07-31
KR0163306B1 KR0163306B1 (en) 1998-12-01

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KR1019950049660A KR0163306B1 (en) 1995-12-14 1995-12-14 Semiconductor chip package for support of semiconductor chip by bonding wire

Country Status (2)

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JP (1) JPH09181225A (en)
KR (1) KR0163306B1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH056951A (en) * 1991-06-27 1993-01-14 Toshiba Corp Semiconductor device and manufacturing method thereof
JPH06188333A (en) * 1992-12-17 1994-07-08 Fujitsu Ltd Semiconductor device
JPH09134996A (en) * 1995-11-07 1997-05-20 Matsushita Electron Corp Resin-sealed type semiconductor device and its manufacture
JPH09134993A (en) * 1995-11-08 1997-05-20 Hitachi Ltd Lead frame, semiconductor integrated circuit device using it and its manufacture

Also Published As

Publication number Publication date
JPH09181225A (en) 1997-07-11
KR0163306B1 (en) 1998-12-01

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