JPH09181225A - Semiconductor chip package and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable ultrathin package. SOLUTION: The semiconductor chip package comprises a semiconductor chip 34 having' an active face arranged with a plurality of electrode bonding pads 34, a lead frame 62 including inner leads 64 and dummy tie bars 66, a bonding wire connecting the inner lead 64 electrically with an electrode bonding pad 38, a semiconductor chip 34, and a package drum for sealing the bonding wire and the inner leads 64 and dummy tie bars 66 of lead frame 62. The dummy tie bar 66 comes into substantial contact with two opposite side faces of semiconductor chip 34 thus supporting the semiconductor chip 34 at the time of forming the package body and the bonding wire supports a semiconductor chip 20 mechanically.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package and a method for manufacturing the same, and more particularly to a semiconductor chip package that is mechanically bonded to a lead frame by using only bonding wires without using lead frame pads or adhesives. The present invention also relates to a semiconductor chip package that is electrically connected and a manufacturing method thereof.

[0002]

2. Description of the Related Art Electronic devices using semiconductor elements are being pursued in miniaturization and high functionality, and it is desired to realize high-density semiconductor elements which are small in size and excellent in reliability. Recently, ultra-thin packages (TSOP, UTSOP) having a package thickness of 1 mm or less have been particularly noted because of their excellent reliability and package mounting density.

FIG. 9 is a sectional view of a conventional semiconductor chip package. The semiconductor chip 2 is attached to the lead frame pad 1 (or die pad) using an adhesive 8 such as Ag-epoxy. The electrode bonding pad 3 and the lead 5 provided on the active surface of the semiconductor chip 2 (the surface on which a predetermined circuit element is provided, here the upper surface) are connected by a wire 4, and the semiconductor chip 2 is connected to an external circuit element. (Not shown). The package body 6 for protecting the semiconductor chip 2 from moisture, dust and other physical and chemical impacts is formed by injecting an epoxy mold compound at high temperature and high pressure. The leads 5 are bent into a form (for example, a gull wing shape) for mounting the package on an external substrate (not shown). The components made of different materials, that is, the lead frame made of copper alloy or iron alloy, the semiconductor chip 2 made of silicon, the lead frame pad 1 made of copper or iron alloy, and the package body 6 made of epoxy mold compound are thermally expanded. Since the physical properties such as the coefficient are different, problems may occur in the reliability of the final packaged product.

Therefore, in FIG. 9, a through hole 7 is formed in the central portion of the lead frame pad 1 so that the package body 6 directly contacts the back surface of the semiconductor chip 2. With such a configuration, the bonding force between the semiconductor chip 2 and the package body 6 is strengthened, and the occurrence of package cracks is reduced. However, interfaces between dissimilar materials still exist, and such interfaces are
It can cause defects in ultra-thin packages.

FIG. 10 is a sectional view of a conventional ultra-thin semiconductor chip package using a LOC (Lead-On-Chip) technique. An electrode bonding pad 13 is formed at the center of the active surface of the semiconductor chip 10, and the leads 15 are bonded onto the active surface of the semiconductor chip 10 with an adhesive 18 such as polyimide. After the electrode bonding pad 13 and the lead 15 are connected by the wire 14, the package body 16 is formed. At this time, if the back surface of the semiconductor chip 10 is exposed from the package body 16, the package thickness can be reduced and a part of the semiconductor chip 10 is exposed to the outside, so that the heat dissipation characteristic is also improved. To do. Further, in the LOC package, the leads are arranged above the active surface of the semiconductor chip, so that the area occupied by the lead frame in the package can be reduced. Further, since the electrode bonding pads are arranged in the central portion of the active surface of the chip, the length of the bus between the circuit element and the electrode bonding pad can be made uniform, which is advantageous in high speed operation and noise suppression.

[0006]

However, since the adhesive 18 exists between the lead 15 and the chip 10,
There is a limit to reducing the thickness. Also, the adhesive 18 is
There is a possibility that a lot of stress may be caused in a subsequent package assembly process or a reliability test performed at high temperature and high pressure to cause a defect. However, the adhesive 18 is used during wire bonding or other assembly process (for example, molding process).
Since it serves to fix the semiconductor chip 10 at times, it is an indispensable constituent element in the conventional package structure.

An object of the present invention is to provide an ultrathin package which is excellent in reliability and has a small thickness. Another object of the present invention is to improve the reliability of the package and reduce the defect rate by reducing the contact interface between different materials as much as possible.

[0008]

SUMMARY OF THE INVENTION A semiconductor chip package according to the present invention is a semiconductor chip having an active surface provided with a plurality of electrode bonding pads, a lead frame having internal leads and dummy tie bars, and the lead frame. Electrical connection means for electrically connecting the internal lead and the electrode bonding pad of the semiconductor chip, and a package body for sealing the semiconductor chip, the electrical connection means, the internal lead of the lead frame and the dummy tie bar. The dummy tie bar substantially contacts two opposite side surfaces of the semiconductor chip to support the semiconductor chip while forming the package body, and the electrical connection means includes the semiconductor chip. The chip is mechanically supported.

In the method of manufacturing a semiconductor chip package according to the present invention, (a) a semiconductor chip having a plurality of electrode bonding pads is separated from a wafer, and (b) the separated semiconductor chip is chip-supported. Temporarily fixing to the base, (c) transferring the chip support to which the semiconductor chip is fixed to a lead frame having a plurality of internal leads, and (d) semiconductor fixed to the chip support. The method includes aligning the chip and the lead frame, and (e) bonding wires to the plurality of electrode bonding pads and the plurality of inner leads.

[0010]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view of an ultrathin semiconductor chip package having an LOC structure according to the present invention. The leads 25 are arranged on the upper side of the semiconductor chip 20 provided with the electrode bonding pads 23, and are connected by the wires 24. The configuration of FIG. 1 is different from that of FIG.
There is no adhesive between the active surface of the chip and the chip 20. Generally, a desired circuit element is formed by wafer processing, and a passivation layer made of silicon nitride (Si ₂ N ₄ ) is applied to the active surface of a semiconductor chip that has undergone the metal wiring process, and a polyimide layer is further applied to the upper surface thereof. Coat to protect the chip surface. Therefore, as in the present invention, even if the insulating adhesive is not present, the lead 2
No electrical short circuit between circuit elements due to 5 occurs. When the connection between the chip and the lead is completed by wire bonding,
Mold resin is injected to form the package body 26.

In the semiconductor assembly process, generally, a semiconductor chip (= die) is selected from a wafer and the selected die is attached to a pad of a lead frame, or in the case of a LOC package, the selected die is attached with an adhesive. Using the die mounting process to attach to the lower surface of the lead of the lead frame,
A wire bonding process for connecting the chip and the lead of the lead frame with a wire of gold or aluminum, a molding process for forming the package body to protect the chip, and an external lead for conforming to the circuit board on which the package is mounted. And an external lead bending step of bending. Here, the lead frame pad and the adhesive support the semiconductor chip during the wire bonding process and prevent the semiconductor chip from being displaced from its original position by the molding resin injected at high pressure during the molding process. It plays a role of fixing. Therefore, as in the present invention,
There are some technical problems to be solved when a means for fixing a semiconductor chip, that is, a lead frame pad or an adhesive is not used during the assembly process.

First, since a means for supporting the semiconductor chip is required during the wire bonding process, in the present embodiment, a wire bonding apparatus having a chip supporting base for fixing the individual die separated from the wafer is used. To do. This chip support can be linearly and rotationally moved not only in the x- and y-axis directions but also in the z-axis direction by a spindle motor. In addition, the chip support is used to support the semiconductor chip during the wire bonding process and is not used in the subsequent processes, such as the molding process, and thus serves to temporarily fix the die. A plurality of vacuum holes are formed in the upper surface of the chip support, a semiconductor chip is placed on the upper surface of the support, and the interface between the chip and the support is evacuated through the vacuum holes. After the semiconductor chip is fixed to the chip support by the suction force, the wire bonding process is performed. When the wire bonding process is completed, the vacuum is released and the semiconductor chip is transferred to the next process. The wire bonding process is performed while the semiconductor chip is fixed to the chip support, so the correct position of the chip can be determined by the CCD (ChargeC
After being recognized by the camera, the spindle motor is controlled based on this position information to move the chip support so that the leads of the lead frame and the chip support are accurately aligned.

Second, the semiconductor chip must be kept in its original position during the molding process for forming the package body. Generally, in a plastic assembly process, a transfer molding process is often used, but this involves placing a lead frame and a semiconductor chip in a cavity formed by an upper mold and a lower mold,
The molten mold resin is injected at high pressure.
Such a high voltage causes a displacement of the chip when there is no special means for fixing the semiconductor chip as in the present invention and the chip is supported only by the bonding wire. On the other hand, a dummy tie bar is formed on the lead frame, and the dummy tie bar is substantially in contact with two opposite side surfaces of the semiconductor chip so that the semiconductor chip can withstand a horizontal impact. . Further, by controlling the direction of the injected mold resin, the impact that the semiconductor chip receives in the vertical direction is controlled.

FIG. 2 is a schematic view of a wire bonding apparatus suitable for manufacturing a semiconductor chip package according to the present invention. In the wire bonding apparatus according to the present embodiment, the conventional die attaching step and wire bonding step are performed in one work line. A large number of wafers 31 are loaded in the wafer loading box 32, and each of the wafers 31 is displayed as being classified into a good chip and a defective chip by an electrical characteristic inspection, and scribing is performed for each individual semiconductor chip. (scribing), and the tape is attached to the back surface of the wafer. Wafer 31
After transferring the wafer to the support ring 33, the chip 34 is removed from the tape (not shown) on the wafer. Chip transfer tool 30
Picks up the individual chips 34 separated from the wafer by the collet 35, moves the transfer plate 37 connected to the collet 35 along the transfer groove 36, and moves the semiconductor chip 34 to the die recognition / transfer section 40. To move.

The die recognition / transfer section 40 includes a spindle motor 41, a chip support 42, and a CCD camera 43. The semiconductor chip 3 by the chip transfer tool 30
When 4 is placed on the chip support 42, the space between the chip 34 and the chip support is evacuated through the vacuum holes 45.
The semiconductor chip 34 is fixed by this vacuum suction force. The position of the fixed chip 34 is recognized by the CCD camera 43, and the spindle motor 4 is detected based on the recognized position information.
1 to control the semiconductor chip 34 at the bonding position BP.
Transfer to The lead frame 62 moves from the loading magazine 60 along the index rail 61 to the bonding position BP. When the lead frame 62 and the chip 34 are located at the bonding position BP, the CCD camera 43 recognizes the positions of the lead frame 62 and the semiconductor chip 34, and then controls the spindle motor 41 to perform accurate alignment. When the alignment is completed, the bonding head 50 bonds the electrode bonding pad of the semiconductor chip 34 and the lead of the lead frame 62 with a wire. The wire-bonded lead frame and semiconductor chip are housed in the unloading magazine 70 and moved to the next assembly process.

FIG. 3 is a schematic view for explaining the wire bonding process according to the present invention. The bonding head 50 includes a body 51, a capillary 52, and a clamp 5
3 and the gold or aluminum wire 55 wound around the reel 54 is connected to the capillary 52. A high voltage of 3000 volts or more is applied to the tip of the wire 55 passing through the capillary 52 to form a wire ball. The wire ball is attached to the electrode bonding pad 38 of the semiconductor chip 34. further,
The wire 55 is guided to the inner lead 64 of the lead frame 62 and wedge-bonded. When the clamp 53 cuts the remaining part of the wire bonded to the inner lead 64, the bonding between the electrode bonding pad and the lead is completed. At this time, the semiconductor chip 34
Are fixed by the chip support 42 of the die recognition / transfer unit 40, as shown in FIG.

In FIG. 3, in order to illustrate the chip support 42, the case where the electrode bonding pads 38 are arranged at the end of the active surface of the semiconductor chip 34 is shown.
In order to realize the LOC structure as shown in FIG. 1, the electrode bonding pad 38 is arranged in the center of the active surface of the chip 34, and the internal lead 64 is located above the active surface of the chip 34.

In FIG. 3, the hole 6 of the lead frame 62 is shown.
Reference numeral 3 is a transfer hole used when the index rail 61 transfers the lead frame 62. Reference numeral 66 indicates a dummy tie bar of the lead frame, which will be described later.

FIG. 4 is a plan view of a molding path system of a transfer molding apparatus suitable for a manufacturing process of a plastic package for forming a protective package body according to the present invention.

The molten mold resin contained in a predetermined container enters the pot 81 by the pressure of the piston (not shown) of the molding apparatus, and passes through the first molding path 82 and the second molding path 83, respectively. It is injected into the cavity 84. Of course, the lead frame to which the semiconductor chip is attached exists in the cavity 84. The cavity 84 is
A package body is formed in the form of lower and upper molds (87 and 88 in FIG. 5) while having a pouring port and the molding resin filling the cavity 84 through the pouring port. The time from the pot 81 to the cavity 84 is usually within a few seconds, and the larger the number of cavities, the more chips can be molded at one time.
The higher pressure must be applied.

FIG. 5 is a cross-sectional view taken along line AA of FIG.

The back surface of the semiconductor chip 34 is in contact with the lower die 87 to form the body of the ultra-thin LOC package as shown in FIG. The leads of lead frame 62 are located above the active surface of chip 34 and are connected to the chip only by wires, there is no adhesive in conventional LOC packages. After the upper mold 88 and the lower mold 87 are fitted together, a mold resin is injected through the injection port 86 along the arrow shown in the figure. At this time, the air contained in the cavity 84 escapes to the outside through an air outlet (not shown).

The semiconductor chip 34 is supported by wires, but its supporting force is not strong enough to withstand the shock received by the molding resin injected at high pressure. Therefore, the lead frame 62 of the present embodiment
Then, as shown in FIG. 6, dummy tie bars 66 are formed on both sides of the chip 34 along the arrangement direction of the injection port. The dummy tie bar 66 has a space D from the side surface of the chip.
Having. The distance D should be determined in consideration of the limit accuracy when aligning the semiconductor chip and the lead frame in the wire bonding process, but it is necessary to prevent damage to the bonding wire even if the chip is moved by the molding resin. Adequate limits must also be taken into consideration. The dummy tie bar 66 prevents the semiconductor chip from moving in the horizontal direction in which the mold resin is injected, that is, in the Y-axis direction in FIG. Since the movement in the X-axis direction is perpendicular to the injection direction of the mold resin, it can be sufficiently prevented by the bonding wire. Regarding the movement in the Z-axis direction, since the semiconductor chip 34 is arranged on the upper surface of the lower mold 87 and the molding resin is injected downward, the chip is stable. At this time, the inlet should be located in the middle or the upper part.

FIG. 7 shows another embodiment of the present invention,
6 is a schematic view illustrating a molding process for forming a package body having a general LOC structure, in which an injection port is located in a lower portion. FIG.

The semiconductor chip 34 is electrically and mechanically connected to the leads of the lead frame 62 by bonding wires. As shown in FIG. 6, the lead frame has a dummy tie bar so that the semiconductor chip can withstand a horizontal impact. However, FIG.
Unlike the case of, the back surface of the semiconductor chip is the lower mold 87.
Since it is not in contact with, it is necessary to consider the impact on the chip in the vertical direction. In this embodiment, the injection port is located at the lower part to reduce the impact of the lead frame 62 on the semiconductor chip. This is the conventional TAB
This is the same as the package transfer molding process using (Tape Automated Bonding).

In the package device using the LOC structure, the dummy tie bar must be stepped so that the dummy tie bar substantially contacts two opposite side surfaces of the semiconductor chip.

FIG. 8 is a schematic view for explaining a molding process for forming a package body having a general structure, in which an injection port is located at an upper portion, according to another embodiment of the present invention.

This is similar to FIG.
Since the back surface of the semiconductor chip is in contact with the lower die 87, the back surface of the semiconductor chip is exposed to the outside after the packaging is completed. However, in the case of the LOC structure as shown in FIG. However, the semiconductor chip package has a general structure. As in the case of FIG. 7, a horizontal impact due to the molding resin is prevented by the dummy tie bar. Since the injection port 86 is located in the upper mold 88, the molding resin is injected from the upper part of the cavity 84. Therefore, the semiconductor chip 34 mounted on the upper surface of the lower mold 87 is not affected by the vertical component of the molding resin.

[0030]

As described above, according to the present invention, a package having a general structure does not use a lead frame pad, and a package having a LOC structure does not use an adhesive, and only a bonding wire is used. The semiconductor chip is supported by and the contact interface between different materials is reduced as much as possible, so that the reliability of the package can be improved. Further, since the semiconductor chip is in direct contact with the mold resin, the bonding force between the mold resin and the semiconductor chip is strengthened, and the generation of package cracks can be suppressed. Further, in the present invention, it is possible to manufacture using the conventional equipment, and it is possible to reduce the manufacturing cost as compared with the one using the TAB method.
Does not require advanced technology.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an ultra-thin semiconductor chip package having a LOC structure according to the present invention.

FIG. 2 is a schematic view of a wire bonding apparatus suitable for manufacturing a package according to the present invention.

FIG. 3 is a schematic view for explaining a wire bonding process according to the present invention.

FIG. 4 is a plan view of a molding path system of a transfer molding apparatus suitable for a manufacturing process of a plastic package for forming a protective package body according to the present invention.

5 is a cross-sectional view taken along the line AA of FIG.

FIG. 6 is a plan view of a lead frame having a dummy tie bar according to the present invention.

FIG. 7 illustrates another embodiment of the present invention, a general LO
FIG. 6 is a schematic view for explaining a molding process in which an injection port is located in a lower part to form a package body having a C structure.

FIG. 8 is a schematic view for explaining a molding process in which an injection port is located at an upper part to form a package body having a general structure according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view of a conventional semiconductor chip package.

FIG. 10 is a cross-sectional view of a conventional ultra-thin semiconductor chip package using LOC technology.

[Explanation of symbols]

 20, 34 Semiconductor Chip 23 Electrode Bonding Pad 24 Bonding Wire 25 Lead 26 Package Body 30 Chip Transfer Tool 40 Die Recognition / Transfer Section 41 Spindle Motor 42 Chip Support 43 CCD Camera 50 Bonding Head 52 Capillary 62 Lead Frame 66 Dummy Tie Bar 70 Anne Loading magazine 81 Pot 82 First molding path 83 Second molding path 84 Cavity 86 Pouring port 87 Lower mold 88 Upper mold

Claims (12)

[Claims] 1. A semiconductor chip having an active surface provided with a plurality of electrode bonding pads, a lead frame including internal leads and a dummy tie bar, and an electrical connection electrically connecting the internal leads and the electrode bonding pads. And a package body for sealing the semiconductor chip, the electrical connection means, the internal leads of the lead frame, and the dummy tie bar, the dummy tie bar facing the semiconductor chip.
A semiconductor chip package, wherein the semiconductor chip is supported while forming the package body by being substantially in contact with a side surface, and the electrical connection means mechanically supports the semiconductor chip. 2. The plurality of electrode bonding pads are
The semiconductor chip package according to claim 1, wherein the semiconductor chip package is arranged at an end of an active surface of the semiconductor chip, and the electrical connection means is a bonding wire. 3. The semiconductor chip package according to claim 2, wherein the package body is formed by a transfer molding process of injecting a high temperature liquid mold compound into the cavity through an injection port. 4. The semiconductor chip package according to claim 3, wherein the injection port is located above the cavity, and a back surface of the semiconductor chip is exposed from the package body. 5. The plurality of electrode bonding pads are
The inner leads of the lead frame are arranged in a central portion of an active surface of the semiconductor chip, the inner leads are located above the active surface of the semiconductor chip, and the electrical connection means is a bonding wire. The semiconductor chip package according to claim 1. 6. The semiconductor chip package according to claim 5, wherein the package body is formed by a transfer molding process in which a high temperature liquid mold compound is injected into the cavity through an injection port. 7. The semiconductor chip package according to claim 6, wherein the injection port is located in a lower portion of the cavity. 8. The semiconductor chip package according to claim 6, wherein the active surface of the semiconductor chip is coated with polyimide. 9. The semiconductor chip package of claim 5, wherein a back surface of the semiconductor chip is exposed from the package body. 10. (a) separating a semiconductor chip having a plurality of electrode bonding pads from a wafer, (b) temporarily fixing the separated semiconductor chip to a chip support, (c) ) Transferring the chip supporting base to which the semiconductor chip is fixed to a lead frame having a plurality of internal leads, and (d) aligning the semiconductor chip fixed to the chip supporting base with the lead frame. e) Bonding wires to the plurality of electrode bonding pads and the plurality of inner leads. A method of manufacturing a semiconductor chip package, the method comprising: 11. A vacuum hole is formed in the chip support, and the step of temporarily fixing the separated semiconductor chip to the chip support includes applying a vacuum through the vacuum hole. 11. The method for manufacturing a semiconductor chip package according to claim 10, which is achieved by: 12. The transfer to the chip support and the alignment of the semiconductor chip and the lead frame are performed by an optical camera that recognizes the positions of the semiconductor chip and the lead frame and a motor controlled by the camera. The method for manufacturing a semiconductor chip package according to claim 10.