KR970053636A - Chip-Sized Semiconductor Package Using Flip Chip Technology - Google Patents

Chip-Sized Semiconductor Package Using Flip Chip Technology Download PDF

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Publication number
KR970053636A
KR970053636A KR1019950058807A KR19950058807A KR970053636A KR 970053636 A KR970053636 A KR 970053636A KR 1019950058807 A KR1019950058807 A KR 1019950058807A KR 19950058807 A KR19950058807 A KR 19950058807A KR 970053636 A KR970053636 A KR 970053636A
Authority
KR
South Korea
Prior art keywords
chip
semiconductor package
kappa
substrate
circuit board
Prior art date
Application number
KR1019950058807A
Other languages
Korean (ko)
Other versions
KR100411810B1 (en
Inventor
유덕수
Original Assignee
황인길
아남산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 황인길, 아남산업 주식회사 filed Critical 황인길
Priority to KR1019950058807A priority Critical patent/KR100411810B1/en
Publication of KR970053636A publication Critical patent/KR970053636A/en
Application granted granted Critical
Publication of KR100411810B1 publication Critical patent/KR100411810B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

본 발명은 반도체칩의 실키기 정도로 제조되는 CSP(Chip Size Package)에 관한 것으로, 플립칩(Flip Chip) 기술을 이용한 반도체칩(4)을 필름부재(2)에 직접 접착하는 즉, 필름부재(2)를 구성하는 회로패턴이 인쇄된 카파회로판(3)에 반도체칩의 펌프(4a)를 직접 접속하는 방법을 채용함으로써 칩 사이즈 크기의 패키지인 CSP를 제공할 수 있는 것이며, 나아가 본 발명은 전자기기에 적용한 경우에는 기기의 소형화, 박형화 및 다기능화까지도 그 실현이 가능해질 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package (CSP) that is manufactured to be about the size of a semiconductor chip, and directly adheres the semiconductor chip 4 using the flip chip technology to the film member 2, that is, the film member ( 2) By adopting a method of directly connecting the pump 4a of the semiconductor chip to the kappa circuit board 3 printed with the circuit pattern constituting the circuit pattern, it is possible to provide a CSP, which is a package of chip size, and furthermore, the present invention provides In the case of application to the device, the device can be miniaturized, thinned and multifunctional.

Description

플립칩(Flip Chip) 기술을 이용한 칩 크기형 반도체패키지Chip-Sized Semiconductor Package Using Flip Chip Technology

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 구성도.1 is a block diagram of the present invention.

Claims (3)

바닥에는 전기단자(1a)가 일정 패턴으로 배열되고 있고, 캔형상을 한 기판(1)과; 상기 기판(1)의 내바닥면에 취부되며, 저면에는 카파회로판(3)이 접착되고, 필름몸체(2a)에는 다수개의 범프홀(2b)이 천공된 비전도성 물질의 필름부재(2)와, 상기 필름부재(2)에 접착되며 필름몸체(2a)에 천공된 펌프홀(2b)을 통해 카파회로판(3)에 접속되는 범프(4a)를 구비한 반도체칩(4)과, 상기 기판(1)과 실장된 반도체칩(4)과의 공간에 충진되는 코팅물질(5)로 구성됨을 특징으로 하는 플림칩(Filp Chip) 기술을 이용한 칩 크기형 반도체패키지.An electric terminal 1a is arranged in a predetermined pattern on the bottom thereof, and has a can-shaped substrate 1; The kappa circuit board 3 is attached to the inner bottom surface of the substrate 1, and the kappa circuit board 3 is adhered to the bottom surface, and the film body 2a is formed of a film member 2 of a non-conductive material having a plurality of bump holes 2b perforated therein. And a semiconductor chip (4) having a bump (4a) attached to the film member (2) and connected to the kappa circuit board (3) through a pump hole (2b) perforated in the film body (2a), and the substrate ( A chip size semiconductor package using a Film Chip technology, characterized in that it comprises a coating material (5) filled in the space between 1) and the mounted semiconductor chip (4). 제1항에 있어서, 기판(1)의 바닥면에서 설치되는 전기단자(1a)를 니켈이나 금으로 도금 처리된 부재를 사용함으로 특징으로 하는 칩 크기형 반도체패키지.The chip size semiconductor package according to claim 1, wherein the electric terminal (1a) provided on the bottom surface of the substrate (1) is made of a member plated with nickel or gold. 제1항에 있어서, 기판(1)에 설치된 전기단자(1a)에 회로패턴이 인쇄된 카파회로판(3)을 접착시킴에 있어서 필름부재(2)를 사용하지 않고 직접 접착시키는 것을 특징으로 하는 칩 크기형 반도체패키지.The chip according to claim 1, wherein in bonding the kappa circuit board 3 on which the circuit pattern is printed to the electrical terminal 1a provided on the substrate 1, the chip is directly bonded without using the film member 2. Size semiconductor package. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950058807A 1995-12-27 1995-12-27 Chip size type semiconductor package using flip chip technique KR100411810B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950058807A KR100411810B1 (en) 1995-12-27 1995-12-27 Chip size type semiconductor package using flip chip technique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950058807A KR100411810B1 (en) 1995-12-27 1995-12-27 Chip size type semiconductor package using flip chip technique

Publications (2)

Publication Number Publication Date
KR970053636A true KR970053636A (en) 1997-07-31
KR100411810B1 KR100411810B1 (en) 2004-03-31

Family

ID=37422919

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950058807A KR100411810B1 (en) 1995-12-27 1995-12-27 Chip size type semiconductor package using flip chip technique

Country Status (1)

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KR (1) KR100411810B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100536886B1 (en) * 1998-02-11 2006-05-09 삼성전자주식회사 Chip scale package and method for manufacturing thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59218762A (en) * 1983-05-26 1984-12-10 Fujitsu Ltd Mounting method of leadless chip carrier
JPH01235261A (en) * 1988-03-15 1989-09-20 Hitachi Ltd Semiconductor device and manufacture thereof
JPH0410635A (en) * 1990-04-27 1992-01-14 Shimadzu Corp Flip chip package mounting
JPH05304246A (en) * 1992-04-28 1993-11-16 Nitto Denko Corp Connector for mounting multi-chip module and mounting structure employing connector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100536886B1 (en) * 1998-02-11 2006-05-09 삼성전자주식회사 Chip scale package and method for manufacturing thereof

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Publication number Publication date
KR100411810B1 (en) 2004-03-31

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