KR970053637A - Chip Size Semiconductor Package - Google Patents

Chip Size Semiconductor Package Download PDF

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Publication number
KR970053637A
KR970053637A KR1019950058809A KR19950058809A KR970053637A KR 970053637 A KR970053637 A KR 970053637A KR 1019950058809 A KR1019950058809 A KR 1019950058809A KR 19950058809 A KR19950058809 A KR 19950058809A KR 970053637 A KR970053637 A KR 970053637A
Authority
KR
South Korea
Prior art keywords
chip
bonded
semiconductor package
semiconductor chip
size
Prior art date
Application number
KR1019950058809A
Other languages
Korean (ko)
Other versions
KR100411809B1 (en
Inventor
이선구
Original Assignee
황인길
아남산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 황인길, 아남산업 주식회사 filed Critical 황인길
Priority to KR1019950058809A priority Critical patent/KR100411809B1/en
Publication of KR970053637A publication Critical patent/KR970053637A/en
Application granted granted Critical
Publication of KR100411809B1 publication Critical patent/KR100411809B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

본 발명은 반도체칩의 실크기 정도로 제조되는 반도체패키지인 CSP에 관한 것으로, 본 발명에서는 패키지형태는 BGA이며, 패키지 사이즈를 거의 칩사이즈의 크기에 해당하는 새로운 반도체 패키지인 CSP를 창안함으로써, 전자기기의 소형화, 박형화, 다기능화의 실현을 가능토록 함과 동시에 휴대용 전자기기의 범용화 및 컴퓨터 기기의 기술 혁신을 꾀할 수 있도록 한 획기적인 발명이다.The present invention relates to a CSP, which is a semiconductor package manufactured to a silk size of a semiconductor chip, and in the present invention, the package form is BGA, and by inventing a CSP, a new semiconductor package whose package size is almost the size of a chip, It is a revolutionary invention that enables the miniaturization, thinning, and multifunctionalization of portable electronic devices, and enables the generalization of portable electronic devices and technological innovation of computer devices.

Description

칩 크기형 반도체패키지.Chip size semiconductor package.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 구성도이다.1 is a block diagram of the present invention.

Claims (3)

겉면에 보호막(1a)이 입혀진 반도체칩(1)과; 상기 반도체칩(1)에 접착 연결되며, 상기 반도체칩(1)의 입출력 패턴과 동일한 패턴의 범프(2c)를 형성한 전도성 테이프(2)와; 상기 전도성 테이프(2)에 접착되며 열압착시 압착죈 부분만이 통전되는 성질을 갖는 이방성 접착재인 ACF(3)와; 상기 ACF(3)에 접착되며 저면으로 다수의 솔더볼(4a)이 부착된 기판(4)과; 상기 기판(4)과 반도체칩(1)의 측면부에 코팅물질(5)을 코팅함으로써 칩 사이즈 크기의 패키지를 구성토록 함을 특징으로 하는 칩 크기형 반도체패키지.A semiconductor chip 1 having a protective film 1a coated on its outer surface; A conductive tape (2) adhesively connected to the semiconductor chip (1) and forming bumps (2c) having the same pattern as the input / output pattern of the semiconductor chip (1); An ACF (3) which is bonded to the conductive tape (2) and is an anisotropic adhesive material having a property that only a pressed part is energized when thermally compressed; A substrate 4 bonded to the ACF 3 and having a plurality of solder balls 4a attached to the bottom thereof; A chip size semiconductor package, characterized in that to configure a chip size package by coating a coating material (5) on the side of the substrate (4) and the semiconductor chip (1). 제1항에 있어서, 전도성 테이프(2)는 폴리이미드필름이 몸체(2a)로 구성되고, 이 몸체(2a)의 일측 상면에는 카파포일(2b)이 일정 패턴을 이루며 접착되어 있고, 이 카파포일(2b)은 몸체(2a)를 관통하는 전도성 금속인 범프(2c)에 의해 전기적인 통전이 가능하도록 한 구조로 구성됨을 특징으로 하는 칩 크기형 반도체패키지.The method of claim 1, wherein the conductive tape 2 is a polyimide film is composed of a body (2a), the upper surface of one side of the body (2a) kappa foil (2b) is bonded in a predetermined pattern, the kappafoil (2b) is a chip-size semiconductor package, characterized in that the structure is configured to enable electrical conduction by the bump (2c) is a conductive metal penetrating the body (2a). 제1항에 있어서, 반도체칩(1)이 접착된 전도성 테이프(2)와 기판(4)의 사이에 전도성 수지(6)를 접착함을 특징으로 하는 칩 크기형 반도체패키지.The chip size semiconductor package according to claim 1, wherein a conductive resin (6) is bonded between the conductive tape (2) to which the semiconductor chip (1) is bonded and the substrate (4). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950058809A 1995-12-27 1995-12-27 Chip size type semiconductor package KR100411809B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950058809A KR100411809B1 (en) 1995-12-27 1995-12-27 Chip size type semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950058809A KR100411809B1 (en) 1995-12-27 1995-12-27 Chip size type semiconductor package

Publications (2)

Publication Number Publication Date
KR970053637A true KR970053637A (en) 1997-07-31
KR100411809B1 KR100411809B1 (en) 2004-03-31

Family

ID=37422918

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950058809A KR100411809B1 (en) 1995-12-27 1995-12-27 Chip size type semiconductor package

Country Status (1)

Country Link
KR (1) KR100411809B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100447895B1 (en) * 1997-09-13 2004-10-14 삼성전자주식회사 Chip scale package having reduced size corresponding to size of semiconductor chip and fabricating method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020058201A (en) * 2000-12-29 2002-07-12 마이클 디. 오브라이언 Semiconductor package and its manufacturing method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01235261A (en) * 1988-03-15 1989-09-20 Hitachi Ltd Semiconductor device and manufacture thereof
JPH0410635A (en) * 1990-04-27 1992-01-14 Shimadzu Corp Flip chip package mounting
JP2835145B2 (en) * 1990-05-28 1998-12-14 株式会社東芝 Electronic equipment
JPH05304246A (en) * 1992-04-28 1993-11-16 Nitto Denko Corp Connector for mounting multi-chip module and mounting structure employing connector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100447895B1 (en) * 1997-09-13 2004-10-14 삼성전자주식회사 Chip scale package having reduced size corresponding to size of semiconductor chip and fabricating method thereof

Also Published As

Publication number Publication date
KR100411809B1 (en) 2004-03-31

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