KR970053000A - Manufacturing method of bipolar transistor - Google Patents
Manufacturing method of bipolar transistor Download PDFInfo
- Publication number
- KR970053000A KR970053000A KR1019950050530A KR19950050530A KR970053000A KR 970053000 A KR970053000 A KR 970053000A KR 1019950050530 A KR1019950050530 A KR 1019950050530A KR 19950050530 A KR19950050530 A KR 19950050530A KR 970053000 A KR970053000 A KR 970053000A
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- film
- emitter
- base
- insulating film
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract 4
- 239000010408 film Substances 0.000 claims abstract 47
- 239000010409 thin film Substances 0.000 claims abstract 40
- 239000012535 impurity Substances 0.000 claims abstract 16
- 238000000034 method Methods 0.000 claims abstract 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract 9
- 239000010703 silicon Substances 0.000 claims abstract 9
- 238000005530 etching Methods 0.000 claims abstract 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract 6
- 238000001312 dry etching Methods 0.000 claims abstract 5
- 238000010438 heat treatment Methods 0.000 claims abstract 4
- 238000005468 ion implantation Methods 0.000 claims abstract 4
- 239000002184 metal Substances 0.000 claims abstract 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- 238000009826 distribution Methods 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 238000011065 in-situ storage Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000000969 carrier Substances 0.000 abstract 2
- 238000002347 injection Methods 0.000 abstract 2
- 239000007924 injection Substances 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000001035 drying Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
본 발명은 자기정렬(self-align) 방법에 의한 쌍극자 트랜지스터의 제조방법에 관한 것으로서, 그 특성은 바이폴러 트랜지스터의 제조방법에 있어서, 규소 기판 위에 제 1 절연막 패턴을 형성하고 제 1 전도형 불순물을 이온주입하고 열처리하여 매몰층을 형성하는 제 1 공정과, 상기 웨이퍼 상에 제 2 절연막으로 소정의 활성영역을 정의하고 제 1 전도형 불순물이 첨가된 단결정 규소 박막을 선택적으로 성장시키고 감광막을 마스크로 컬렉터 싱커 부분에 고농도로 제 1 전도형 불순물을 첨가하는 제 2 공정과, 상기 감광막을 제거하고 웨이퍼 전면에 완충용 규소 박막과 제 2 전도형 불순물이 첨가된 베이스 박막을 순차적으로 성장시킨 다음 제 1 전도형 불순물이 첨가된 에미터 박막과 제 3 절연막을 순차적으로 적층하고 감광막으로 에미터를 정의하고 절연막과 에미터 박막을 순차적으로 건식식각한 다음 비활성 베이스영역에 제 2 전도형 불순물을 이온주입하는 제 3 공정과, 상기 감광막을 제거하고 베이스 전극부분을 감광막으로 정의하고 베이스 박막과 규소 박막을 건식식각하는 제 4 공정과, 상기 감광막을 제거하고 웨이퍼 전면에 제 4 절연막을 적층한 후 열처리하여 에미터 박막내의 불순물을 확산시켜 에미터를 형성하고 감광막으로 베이스 전극부분을 정의하는 제 5 공정과, 상기 감광막을 마스크로 하여 제 4 절연막을 건식식각하여 에미터 박막의 측면에 측면절연막을 형성함과 동시에 베이스 전극이 형성되는 부분의 절연막을 식각하여 베이스 박막을 노출시킨 후 제 2 전도형 불순물을 고농도로 이온주입하는 제 6 공정과, 상기 감광막을 제거하고 노출된 베이스 박막 상에 선택적으로 베이스 전극용 박막을 형성시키고 제 5 절연막을 적층하는 제 7 공정과, 상기 절연막을 평탄화하여 에미터 박막 위의 제 5 절연막을 제거하여 에미터 박막 위의 제 3 절연막을 노출시키는 제 8 공정과, 상기 노출된 제 3 절연막을 식각하여 에미터 접점을 형성하는 제 9 공정과, 감광막으로 베이스와 컬렉터 접점을 정의하고 절연막을 식각하여 접점을 형성하는 제 10 공정 및 상기 감광막을 제거하고 금속 전극을 형성하는 제 1 공정을 포함하는 데에 있으므로, 본 발명은 규소 게르마늄을 베이스로 사용하여 에미터(Emitter)와 베이스의 에너지 띠의 차이(energy bandgap)에 의해 전위장벽이 형성되어 에미터에서 베이스로의 반송자(carrier)의 주입은 증가되는 반면 베이스에서 에미터로의 반송자의 주입은 차단되어 결과적으로 전류이득이 증가되는 데에 그 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a dipole transistor by a self-aligning method. The characteristics of the method of manufacturing a bipolar transistor include: forming a first insulating film pattern on a silicon substrate and forming a first conductivity type impurity A first step of forming a buried layer by ion implantation and heat treatment, defining a predetermined active region as a second insulating film on the wafer, selectively growing a single crystal silicon thin film to which a first conductivity type impurity is added, and using a photoresist as a mask A second step of adding a first conductivity type impurity to the collector sinker portion at a high concentration; and removing the photosensitive film, and growing a buffered silicon thin film and a base thin film to which the second conductivity type impurity is added on the entire surface of the wafer, and then The emitter thin film to which the conductivity type impurity is added and the third insulating film are sequentially stacked, and the emitter is defined and insulated from the photosensitive film. A third step of sequentially dry etching the film and the emitter thin film and then ion implanting a second conductivity type impurity into the inactive base region, removing the photosensitive film, defining the base electrode portion as the photosensitive film, and drying the base thin film and the silicon thin film. A fourth process of etching, a fifth process of removing the photoresist film, stacking a fourth insulating film on the entire surface of the wafer, and then heat treatment to diffuse impurities in the emitter thin film to form an emitter and define a base electrode portion as the photoresist film; Dry etching the fourth insulating film using the photosensitive film as a mask to form a side insulating film on the side of the emitter thin film, and etching the insulating film of the portion where the base electrode is formed to expose the base thin film, and then the second conductive impurity concentration is high. A sixth step of ion implantation into the process, and removing the photosensitive film and selectively transferring the base on the exposed base thin film. A seventh step of forming a pole thin film and stacking a fifth insulating film, an eighth step of planarizing the insulating film to remove the fifth insulating film on the emitter thin film to expose the third insulating film on the emitter thin film, and the exposure A ninth step of forming an emitter contact by etching the third insulating film; and a tenth step of defining a base and collector contact with the photosensitive film, and forming a contact by etching the insulating film; and removing the photosensitive film and forming a metal electrode. Since the present invention includes one step, the present invention uses a silicon germanium as a base to form a dislocation barrier formed by an energy bandgap between an emitter and a base, thereby forming a carrier from the emitter to the base. The injection of carriers is increased while the injection of carriers from the base to the emitter is blocked, resulting in an increase in current gain.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 완성된 바이폴러 트랜지스터의 단면도.2 is a cross-sectional view of a completed bipolar transistor according to the present invention.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050530A KR0161200B1 (en) | 1995-12-15 | 1995-12-15 | Method for fabricating bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050530A KR0161200B1 (en) | 1995-12-15 | 1995-12-15 | Method for fabricating bipolar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053000A true KR970053000A (en) | 1997-07-29 |
| KR0161200B1 KR0161200B1 (en) | 1999-02-01 |
Family
ID=19440497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950050530A KR0161200B1 (en) | 1995-12-15 | 1995-12-15 | Method for fabricating bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0161200B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100296707B1 (en) * | 1997-09-23 | 2001-08-07 | 오길록 | Bipolar transistor and method for fabricating the same |
-
1995
- 1995-12-15 KR KR1019950050530A patent/KR0161200B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100296707B1 (en) * | 1997-09-23 | 2001-08-07 | 오길록 | Bipolar transistor and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR0161200B1 (en) | 1999-02-01 |
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