KR970052942A - Reduction of Parasitic Capacitance at Intersection of Metallization in Integrated Circuits Using Heterojunctions - Google Patents

Reduction of Parasitic Capacitance at Intersection of Metallization in Integrated Circuits Using Heterojunctions Download PDF

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Publication number
KR970052942A
KR970052942A KR1019950053681A KR19950053681A KR970052942A KR 970052942 A KR970052942 A KR 970052942A KR 1019950053681 A KR1019950053681 A KR 1019950053681A KR 19950053681 A KR19950053681 A KR 19950053681A KR 970052942 A KR970052942 A KR 970052942A
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South Korea
Prior art keywords
silicon nitride
film
secondary plasma
nitride film
intersection
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KR1019950053681A
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Korean (ko)
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KR0169832B1 (en
Inventor
박문평
이태우
송기문
박성호
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양승택
한국전자통신연구원
이준
한국전기통신공사
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Priority to KR1019950053681A priority Critical patent/KR0169832B1/en
Publication of KR970052942A publication Critical patent/KR970052942A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 이종접합소자를 이용한 집적회로의 공정중 급속배선의 교차점에서 발생하는 기생 커패시턴스를 감소시키는 방법에 관한 것으로서, 리프트 오프(Lift Off)공정에 의해 배선된 1차 금속막 상부에 2차 플라즈마 실리콘 질화막을 형성하는 제1과정과, 상기 2차 플라즈마 실리콘 질화막의 전면에 감광막을 도포하는 제2과정과, 상기 2차 플라즈마 실리콘 질화막의 절연막에 산소이온을 주입하여 무정형 질화실리콘과 무정형 산화실리콘의 혼합물을 형성하는 제3과정 및 리프트 오프 공정에 의해 2차 금속막을 배선하는 제4과정을 포함하여 이루어지며, 산소이온주입에 의해 2차 플라즈마 실리콘 절연막의 유전율을 감소시킴으로써 1차 금속배선과 2차 금속배선의 교차점에서 발생하는 기생 커패시턴스를 줄이고, 이에 따라 집적회로의 밴드폭을 증가시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing parasitic capacitance occurring at the intersection of rapid wiring during an integrated circuit using a heterojunction device, wherein the secondary plasma is formed on a primary metal film wired by a lift off process. A first process of forming a silicon nitride film, a second process of applying a photoresist film to the entire surface of the secondary plasma silicon nitride film, and implanting oxygen ions into the insulating film of the secondary plasma silicon nitride film to form an amorphous silicon nitride and And a fourth process of wiring the secondary metal film by a third process of forming a mixture and a lift-off process, and by reducing the dielectric constant of the secondary plasma silicon insulating film by oxygen ion implantation. Reduce the parasitic capacitance occurring at the intersection of the metal lines, and thus increase the bandwidth of the integrated circuit. There is an effect that it is possible.

Description

이종접합소자를 이용한 집적회로에서 금속배선의 교차점의 기생 커패시턴스를 감소시키는 방법Reduction of Parasitic Capacitance at Intersection of Metallization in Integrated Circuits Using Heterojunctions

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 (a)~(b)는 종래 기술에 따른 제작공정 단면도.1 is a cross-sectional view of the manufacturing process according to the prior art (a) ~ (b).

제2도는 (a)~(c)는 본 발명에 따른 제작공정을 보여주는 단면도.2 is a cross-sectional view showing the manufacturing process according to the present invention (a) ~ (c).

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 1차 플라즈마 증착 절연막(First PECVD Insulating Film)10: First PECVD Insulating Film

11 : 1차 금속막(First Metal Film)11: First Metal Film

12 : 2차 플라즈마 증착 절연막(Second PECVD Insulating Film)12: Secondary PECVD Insulating Film

13 : 감광막(Photoresist Film)13: Photoresist Film

14 : 2차 금속막(Second Metal Film)14: Second Metal Film

Claims (2)

이종접합 바이폴라 트랜지스터를 이용한 집적회로 공정에 있어서, 리프트 오프(Lift Off)공정에 의해 배선된 1차 금속막 상부에 2차 플라즈마 실리콘 질화막을 증착하는 제1과정과; 상기 2차 플라즈마 실리콘 질화막의 전면에 감광막을 도포하는 제2과정과; 상기 2차 플라즈마 실리콘 질화막에 산소이온을 주입하여 무정형 질화실리콘과 무정형 산화실리콘의 혼합물을 형성하는 제3과정 및 리프트 오프 공정에 의해 2차 금속막을 배선하는 제4과정을 포함하여 이루어지는 것을 특징으로 하는 이종접합소자를 이용한 집적회로에서 금속배선의 교차점의 기생 커패시턴스를 감소시키는 방법.An integrated circuit process using heterojunction bipolar transistors, comprising: a first process of depositing a secondary plasma silicon nitride film on a primary metal film wired by a lift off process; A second process of coating a photoresist on the entire surface of the secondary plasma silicon nitride film; And a third process of injecting oxygen ions into the secondary plasma silicon nitride film to form a mixture of amorphous silicon nitride and amorphous silicon oxide and a fourth process of wiring the secondary metal film by a lift-off process. A method for reducing parasitic capacitances of intersection points of metal lines in integrated circuits using heterojunction devices. 제1항에 있어서, 상기 제3과정의 산소이온의 주입시, 상기 산소이온의 테일(tail)영역이 2차 플라즈마 실리콘 질화막과 상기 1차 금속막의 경계면에 오도록 가속에너지를 조절하는 것을 특징으로 하는 이종접합소자를 이용한 집적회로에서 금속배선의 교차점의 기생 커패시턴스를 감소시키는 방법.The method of claim 1, wherein the acceleration energy is adjusted so that the tail region of the oxygen ion is at the interface between the secondary plasma silicon nitride film and the primary metal film when the oxygen ion is injected in the third process. A method for reducing parasitic capacitances of intersection points of metal lines in integrated circuits using heterojunction devices. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950053681A 1995-12-21 1995-12-21 Method for reducing parastic capacitance at crossover in integrated circuit using heterojunction device KR0169832B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950053681A KR0169832B1 (en) 1995-12-21 1995-12-21 Method for reducing parastic capacitance at crossover in integrated circuit using heterojunction device

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Application Number Priority Date Filing Date Title
KR1019950053681A KR0169832B1 (en) 1995-12-21 1995-12-21 Method for reducing parastic capacitance at crossover in integrated circuit using heterojunction device

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KR970052942A true KR970052942A (en) 1997-07-29
KR0169832B1 KR0169832B1 (en) 1999-02-18

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