KR970052775A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR970052775A
KR970052775A KR1019950069491A KR19950069491A KR970052775A KR 970052775 A KR970052775 A KR 970052775A KR 1019950069491 A KR1019950069491 A KR 1019950069491A KR 19950069491 A KR19950069491 A KR 19950069491A KR 970052775 A KR970052775 A KR 970052775A
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KR
South Korea
Prior art keywords
etching
polysilicon
power
initial
gate oxide
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KR1019950069491A
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Korean (ko)
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KR0171989B1 (en
Inventor
백인혁
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김주용
현대전자산업 주식회사
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Priority to KR1019950069491A priority Critical patent/KR0171989B1/en
Publication of KR970052775A publication Critical patent/KR970052775A/en
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Publication of KR0171989B1 publication Critical patent/KR0171989B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 게이트 전극 패턴을 형성하기 위한 건식식각시 게이트 절연막의 파괴를 방지하는 게이트 전극 패턴 식각방법에 관한 것이다. 이와 같은 본 발명의 반도체 소자의 제조방법은 실리콘 기판상에 게이트 산화막과 폴리실리콘을 순차적으로 형성하는 단계; 상기 폴리실리콘 상에 게이트 전극을 형성할 영역에 감광막 패턴을 형성하는 단계; 결과되는 반도체 기판을 플라즈마 챔버 내에 위치시키고 고주파 전력을 인가하여 챔버 내를 플라즈마 상태로 만드는 단계; 상기 폴리실리콘 상의 네이티브 옥사이드를 상기 감광막 패턴의 형태로 건식식각하여 폴리실리콘을 노출시키는 단계; 폴리실리콘 식각을 위한 초기 고주파 전력을 인가하고 상기 고주파 전력을 서서히 감소시키면서 폴리실리콘을 플라즈마 건식식각하는 단계; 상기 플라즈마 챔버를 펌핑시키는 단계; 오버식각을 위한 초기 고주파 전력을 인가하고 게이트 산화막의 소정 %두께까지 식각을 실시하는 단계; 초기 고주파 전력을 소정등분으로 나누어 그 등분값의 전력을 점차적으로 감소시키면서 게이트 산화막을 건식식각하는 단계를 포함하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a gate electrode pattern etching method for preventing destruction of a gate insulating layer during dry etching for forming a gate electrode pattern. Such a method of manufacturing a semiconductor device of the present invention comprises the steps of sequentially forming a gate oxide film and polysilicon on a silicon substrate; Forming a photoresist pattern on a region where the gate electrode is to be formed on the polysilicon; Positioning the resulting semiconductor substrate in a plasma chamber and applying high frequency power to make the chamber into a plasma state; Dry etching the native oxide on the polysilicon in the form of the photoresist pattern to expose the polysilicon; Plasma dry etching polysilicon while applying initial high frequency power for polysilicon etching and gradually decreasing the high frequency power; Pumping the plasma chamber; Applying an initial high frequency power for over etching and etching to a predetermined% thickness of the gate oxide film; And dividing the initial high frequency power into predetermined equal parts and dry etching the gate oxide film while gradually decreasing the power of the equal value.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 바람직한 실시예에 따른 플라즈마 건식식각시 인가되는 고주파 전력의 시간에 따른 단계적 감소를 설명하기 위한 도면.3 is a view for explaining the gradual decrease with time of the high frequency power applied during the plasma dry etching in accordance with a preferred embodiment of the present invention.

Claims (7)

실리콘 기판상에 게이트 산화막과 폴리실리콘을 순차적으로 형성하는 단계; 상기 폴리실리콘 상에 게이트 전극을 형성할 영역에 감광막 패턴을 형성하는 단계; 결과되는 반도체 기판을 플라즈마 챔버 내에 위치시키고 고주파 전력을 인가하여 챔버 내를 플라즈마 상태로 만드는 단계; 상기 폴리실리콘 상의 네이티브 옥사이드를 상기 감광막 패턴의 형태로 건식식각하여 폴리실리콘을 노출시키는 단계; 폴리실리콘 식각을 위한 초기 고주파 전력을 인가하고 상기 고주파 전력을 서서히 감소시키면서 폴리실리콘을 플라즈마 건식식각하는 단계; 상기 플라즈마 챔버를 펌핑시키는 단계; 오버 식각을 위한 초기 고주파 전력을 인가하고 게이트 산화막의 소정 %두께까지 식각을 실시하는 단계; 초기 고주파 전력을 소정등분으로 나누어 그 등분값의 전력을 점차적으로 감소시키면서 게이트 산화막을 건식식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Sequentially forming a gate oxide film and polysilicon on the silicon substrate; Forming a photoresist pattern on a region where the gate electrode is to be formed on the polysilicon; Positioning the resulting semiconductor substrate in a plasma chamber and applying high frequency power to make the chamber into a plasma state; Dry etching the native oxide on the polysilicon in the form of the photoresist pattern to expose the polysilicon; Plasma dry etching polysilicon while applying initial high frequency power for polysilicon etching and gradually decreasing the high frequency power; Pumping the plasma chamber; Applying an initial high frequency power for over etching and etching to a predetermined% thickness of the gate oxide film; And dividing the initial high frequency power into predetermined equal parts and dry etching the gate oxide film while gradually decreasing the power of the equal value. 제1항에 있어서, 상기 폴리실리콘을 플라즈마 건식식각하는 단계는 게이트 산화막이 전체 면적이 10% 내지 30%까지 드러나는 순간까지 초기 전력을 유지하여 식각하는 과정, 전력을 초기 전력의 10% 내지 30%만큼 줄이고 게이트 산화막이 전체 면적의 30% 내지 50%까지 드러날 수 있도록 0.1초 내지 1초 동안 식각하는 과정, 전력을 초기 전력의 30% 내지 50%만큼 줄이고 게이트 산화막이 전체 면적의 50% 내지 80%까지 드러날 수 있도록 0.1초 내지 1초동안 식각하는 과정, 전력을 초기 전력의 50% 내지 80%만큼 줄이고 0.1초 내지 1초 동안 식각하는 과정을 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the plasma dry etching of the polysilicon is performed by maintaining the initial power until the gate oxide layer is exposed to 10% to 30% of the total area, and etching the power by 10% to 30% of the initial power. Etch for 0.1 seconds to 1 second so that the gate oxide is exposed to 30% to 50% of the total area, and reduce the power by 30% to 50% of the initial power, and the gate oxide is 50% to 80% of the total area. Etching for 0.1 seconds to 1 second so as to reveal, a method of manufacturing a semiconductor device comprising the step of reducing the power by 50% to 80% of the initial power for 0.1 seconds to 1 second. 제1항 또는 제2항에 있어서, 상기 폴리실리콘의 플라즈마 건식식각시 공급되는 초기 전력은 200와트 내지 1000와트인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the initial power supplied during plasma dry etching of the polysilicon is in the range of 200 Watts to 1000 Watts. 제1항에 있어서, 상기 오버 식각 단계는 폴리실리콘과 산화막의 선택비가 10:1이상인 식각가스를 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein in the over-etching step, an etching gas having a selectivity of polysilicon and an oxide layer of 10: 1 or more is used. 제1항에 있어서, 상기 오버식각단계는 게이트 산화막의 초기 두께의 약 70%까지 식각을 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the over-etching process comprises etching up to about 70% of the initial thickness of the gate oxide layer. 제1항에 있어서, 게이트 산화막이 식각에 의해 이것의 초기 두께의 70%가 되는 시점부터 60%되는 시점간의 시간을 다섯 등분이상의 값으로 나누고 오버 식각 초기에 걸리는 전력을 상기 시간 등분에 따라 나누어서 게이트 산화막이 게이트 산화막 초기 두께의 70%가 되는 시점부터 각 등분된 시간 간격마다 상기 등분된 전력량만큼 단계적으로 감소시키면서 식각을 진행하고 게이트 산화막의 두께가 게이트 산화막의 초기 두께의 60%가 되는 시점에 맞추어 전원이 차단되도록 하는 것을 특징으로 하는 반도체 소자의 제조방법.2. The method of claim 1, wherein the time between the gate oxide film becoming 70% of its initial thickness by etching and the time when the gate oxide becomes 60% is divided by a value equal to or greater than five equal parts and the power required for the initial over-etching is divided by the time equal parts. From the time when the oxide layer becomes 70% of the initial thickness of the gate oxide layer, the etching is performed while gradually decreasing the equal amount of power at each equal time interval, and when the thickness of the gate oxide layer becomes 60% of the initial thickness of the gate oxide layer. A method of manufacturing a semiconductor device, characterized in that the power is cut off. 제1항 또는 제5항에 있어서 상기 오버식각시 공급되는 초기 전력은 200와트 내지 500와트인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the initial power supplied during the over-etching is 200 Watts to 500 Watts. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069491A 1995-12-30 1995-12-30 Method for manufacturing semiconductor device KR0171989B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100363712B1 (en) * 2000-08-19 2002-12-12 우진환경개발 주식회사 Asphalt-concrete scrap processing and reclaiming equipment and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100363712B1 (en) * 2000-08-19 2002-12-12 우진환경개발 주식회사 Asphalt-concrete scrap processing and reclaiming equipment and method

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