KR970050165A - Descrambler on SD DVD - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a descrambler of an SD DVD that performs descrambling in an SD DVD (Digital Video Disc). Enable) ID register that outputs 4 bits as ID data by inputting 8 bits of data input through the data bus according to the clock signal, and decodes 16 bits of decoded data as input by decoding the ID data output from the ID register. Initial condition according to a reset / set signal generator for decoding a scramble initial number and outputting a 15-bit descramble preset signal, and a reset enable signal input from the outside. Is set and preset according to the descramble preset signal outputted from the reset / set signal generator. It consists of the descrambler 15-bit shift register which shifts the data of eight bits input via the data bus group and to descramble the output descrambled output data. Therefore, the present invention can be implemented according to the standard for SD-DVD and can be implemented with a simple circuit.

Description

Descrambler on SD DVD

As this is a public information case, the full text was not included.

1 is a block diagram of a descrambler of an SD DVD according to the present invention.

2 is a view showing an initial condition of a descramble shift register.

3 is a detailed configuration diagram of the ID resist of FIG.

Claims (8)

8 bits of data inputted through the data bus according to the ID enable clock signal ID-EN which is reset according to an ID-Reset signal input from the outside and input from the outside ( ID register 1 for outputting 4 bits (SDB [6: 3]) as ID data (ID [6: 3]) on input of SDB [7: 0]), and ID output from the ID register 1 An ID register data decoding section 2 that codes the data ID [6: 3] and outputs 16-bit decoded data DEC [15: 0], which is output from the ID register data decoding section 2 A reset / set signal which decodes a descramble initial preset number with the decoded data DEC15: 0 and outputs a 15-bit descramble preset signal (DSC-RS [0:14]). Initial state according to the generation unit 3 and the reset enable signal RES-EN input from the outside (Initial Cond) 8-bit data is set and preset according to the descramble preset signal (DSC-RS [0:14]) output from the reset / set signal generator 3 and input via the data bus. And a 15-bit shift register 4 for descrambling which shifts and descrambles (SDB [7:10]) and outputs descrambling output data (DSC-O [0: 7]). SD DVD descrambler. 2. The ID register 1 according to claim 1, wherein the ID register 1 is reset according to an ID-Reset signal input from the outside and an ID enable clock signal ID-EN input from the outside. To the first flip-flop 11, which outputs the least significant bit (SDB <0>) of the data (SCB7: 0) input through the data bus in synchronization with the data bus, and to an ID-reset signal input from the outside. The lower second bit (SDB <1>) of the data (SDB7: 0) input through the data bus is output in synchronization with the ID enable clock signal (ID-EN). The second flip-flop 12, which is reset according to an ID-Reset signal input from the outside and is synchronized with an ID Enable Clock signal ID-EN input from the outside. Lower third bit (SDB <2>) of data (SDB [7: 0]) input through the bus ) Is output to the third flip-flop 13 and the ID enable clock signal ID-EN, which is reset according to an ID-Reset signal input from the outside and input from the outside. The lower fourth bit SDB <3> of the data SDB [7: 0] input through the data bus in synchronization is output to the ID register data decoding unit 2 as the ID bit ID <3>. The fourth flip-drop 14 is reset in accordance with an ID-Reset signal input from the outside and is synchronized with an ID Enable Clock signal ID-EN input from the outside. A fifth flip-flop that outputs the lower fifth bit SDB <4> of the data SDB [7: 0] to the ID register data decoding unit 2 as an ID bit <ID <4>. (15) An ID enable (Reset) inputted from the outside and reset according to an ID-Reset signal input from the outside The lower sixth bit SDB <5> of the data SDB [7: 0] inputted through the data bus in synchronization with the clock signal ID-EN is referred to as the ID bit ID <5>. The sixth flip-flop 16 outputted to the ID register data decoding section 2 and an ID enable clock that is reset according to an ID-Reset signal input from the outside and input from the outside. Decoding the ID register data from the lower seventh bit SDB <6> of the data SDB [7: 0] input through the data bus in synchronization with the signal ID-EN to the ID bit ID <6>. The seventh flip-flop 17 outputted to the negative unit 2 and an ID enable clock signal (ID) that is reset and input from the outside according to an ID-reset signal input from the outside. And an eighth flip-flop 18 which outputs the most significant bit SDB <7> of the data SDB [7: 0] inputted through the data bus in synchronization with EN). The descrambler of the SD DVD, characterized in that. 2. The first, second, third and fourth portions of claim 1, wherein the ID register data decoding section 2 inverts ID data ID [6: 3] output from the ID register 1, respectively. Fifth, sixth, seventh, and inverting outputs of the inverters 21, 22, 23, 24, and the first, second, third, and fourth inverters 21, 22, 23, 24, and The least significant bit DEC <of the decoded data is negatively multiplied by the outputs of the eighth inverters 25, 26, 27, 28, and the first, second, third, and fourth inverters 21, 22, 23, and 24. 0>) of the first NAND gate 29 and the first, second, third, and eighth inverters 21, 22, 23, and 28 outputting the reset / set signal generator 3 to the reset / set signal generator 3; A second NAND gate 30 for outputting the lower second bit DEC <1> of the decoded data to the reset / set signal generator 3, the first, second, and fourth bits by negative logic multiplication of the output; And negatively multiply the outputs of the seventh inverters 21, 22, 24, and 27 to generate the lower third bit DEC <2> of the decoded data. The fourth NAND gate 31 and the outputs of the first, second, seventh, and eighth inverters 21, 22, 27, and 28 that are output to the negative unit 3 are negative and ORed to be the lower fourth of the decoded data. A fourth NAND gate 32 for outputting a bit DEC <3> to the reset / set signal generator 3, and the first, third, fourth, and sixth inverters 21, 23, and 24; A fifth NAND rate 33 for outputting the lower fifth bit (DEC <4>) of the decoded data to the reset / set signal generator 3 by performing a negative AND on the output of (26). Negative AND of the outputs of the third, sixth, and eighth inverters 21, 23, 26, and 28 to transfer the lower sixth bit DEC <5> of the decoded data to the reset / set signal generator 3. The sixth NAND gate 34 and the outputs of the first, fourth, sixth, and seventh inverters 21, 24, 26, and 27 are negative-ORed to decode the lower seventh bits DEC <6. (7), the first, sixth, seventh, and seventh NAND gates 35 outputting the &quot;) to the reset / set signal generator 3; An eighth NAND gate that negatively multiplies the output of the eighth inverters 21, 26, 27, and 28 and outputs the lower eighth bit DEC <7> of the decoded data to the reset / set signal generator 3. (36). Generating the reset / set signal by negatively multiplying the outputs of the second, third, fourth, and fifth inverters 22, 23, 24, and 25 by decoding the lower ninth bit DEC <8> of the decoded data. Negative AND of the outputs of the ninth NAND gate 37 and the second, third, fifth, and eighth inverters 22, 23, 25, and 28 outputted to the unit 3, and the lower tenth of the decoded data. A tenth NAND gate 38 for outputting a bit DEC <9> to the reset / set signal generator 3, and the second, fourth, fifth, and seventh inverters 22, 24, and 25; , An eleventh NAND gate 39, and the second and the second to output the lower eleventh bit DEC <10> of the decoded data to the reset / set signal generator 3 by performing a negative AND on the output of the &quot; 27 &quot; Negative AND of the outputs of the fifth, seventh, and eighth inverters 22, 25, 27, 28 to transfer the lower twelfth bit DEC <11> of the decoded data to the reset / set signal generator 3 Outputs the outputs of the twelfth NAND gate 40 and the third, fourth, fifth, and sixth inverters 23, 24, 25, and 26. The thirteenth NAND gate 41, the third, fifth, sixth, and negative integers, which output the lower fourteenth bits DEC <12> of the decoded data to the reset / set signal generator 3. A fourteenth NAND gate that outputs the lower fifteenth bit DEC <13> of the decoded data to the reset / set signal generator 3 by performing an AND logic on the outputs of the eighth inverters 23, 25, 26, and 28. (43) negatively multiplies the outputs of the fourth, fifth, sixth, and seventh inverters 24, 26, 27, 28 to reset / set the most significant bit DEC <14> of the decoded data. Negative AND of the outputs of the fifteenth NAND gate 43 and the fifth, sixth, seventh, and eighth inverters 25, 26, 27, and 28 outputted to the signal generator 3 to decode the decoded data. And a sixteenth NAND gate (44) for outputting the most significant bit (DEC <15>) to the reset / set signal generator (3). 2. The reset / set signal generation unit (3) according to claim 1, wherein the reset / set signal generation unit (3) is the lower second, sixth, and ninth of the decoded data (DEC [15: 0]) output from the ID register data decoding unit (2). And a NAND gate 51 that negates AND of the fourteenth bit (DEC <1, 5, 9, 13>) and the most significant bit of the descrambling preset signal by inverting the output of the NAND gate 51 (DSC-RS < 14) the lower inverter of the first inverter 52 outputting to the 15-bit shift register 4 for descramble and the decoding data DEC [15: 0] output from the ID register data decoding section 2; The 15-bit shift register for descrambling to the lower fourteenth set (DSC-RS <13>) of the descrambling preset signal by ANDing the fourth, eighth, and twelfth bits DEC <3, 7, 11>. 4) lower second, sixth, and tenth ratios of the first and gate 53 outputted from the ID register data and the decoded data DEC [15: 0] outputted from the ID register data decoding unit 2; A second end gate outputting the lower 13th bit (DSC-RS <12>) of the descrambling preset signal to the 15-bit shift register 4 for descrambling by logically multiplying (DEC <1, 5, 9>) 54) the lower fourth of the decoded preset signal by ANDing the lower fourth and eighth bits DEC <3, 7> of the decoded data DEC [15: 0] output from the ID register data decoding unit 2; The third end gate 55 outputs the twelfth bit (DSC-RS <11>) to the 15-bit shift register 4 for descrambling, and the decoded data DEC [outputted from the ID register data decoding unit 2. 15 bit shift bit of the lower second and sixth bits (DEC <1, 5>) to the lower eleventh bit (DSC-RS <10>) of the descrambling preset signal. A fourth end gate 56 output to the register 4 and decoded data DEC [15: 0] output from the ID register data decoding section 2; The second inverter 57 for inverting the lower fourth bit DEC <3> and the lower tenth bit DSC-RE <9> of the descrambling preset signal by inverting the output of the second inverter 57. A descrambling preset signal of the third inverter 58 outputted to the 15-bit shift register 4 for descrambling, and the decoded data DEC [15: 0] outputted from the ID register data decoding section 2; A fourth inverter 59 that inverts the lower second bit DEC-RS <1> of the second inverter bit, and a lower ninth bit of the descrambling preset signal by inverting the output of the fourth inverter 59 (DSC-RS <1). 8) the lower inverter of the decoded data DEC [15: 0] output from the fifth inverter 60 and the ID register data decoding section 2 outputting to the 15-bit shift register 4 for descrambling. A sixth inverter 61 that inverts the 15-bit DEC <14>, and an output of the sixth inverter 61 to invert the output of the descrambling preset signal. A seventh inverter 62 outputting the eighth bit (DSC-RS <7>) to the 15-bit shift register 4 for descrambling, and the decoding data DEC [outputted from the ID register data decoding section 2; 15: 0]) the eighth inverter 63 inverting the lower third bit DEC <12> and the lower seventh bit DSC of the descrambling preset signal by inverting the output of the eighth inverter 63. A ninth inverter 64 for outputting the descrambled 15-bit shift register 4 to RS <6>, and the decoded data DEC [15: 0] outputted from the ID register data decoding section 2; The tenth inverter 65 for inverting the lower eleventh bit DEC <10> and the sixth lower bit of the descrambling preset signal by inverting the output of the tenth inverter 65 (DSC-RS <5>). ), The eleventh inverter 66 outputting to the 15-bit shift register 4 for descrambling, and the decoded data outputted from the ID register data decoding section 2 The twelfth inverter 67 inverting the lower ninth bit DEC <8> among the DEC [15: 0], and the lower sixth bit of the descrambling preset signal by inverting the output of the twelfth inverter 67 ( A thirteenth inverter 68 outputting the DSC-RS <4> to the 15-bit shift register 4 for descrambling, and decoded data (DEC [15: 0]) output from the ID register data decoding section 2; Fourteenth inverter 69 for inverting the lower seventh bit DEC <6> and inverting the output of the fourteenth inverter 69 to the fourth lower bit of the descrambling preset signal DSC-RS <3>. The most significant bit and the fifth bit of the fifteenth inverter 70 outputting to the descramble 15 bit shift register 4 and the decoded data DEC [15: 0] output from the ID register data decoding section 2 Multiply (DEC <15,4>) to the lower third bit (DSC-RS <2>) of the descrambling preset signal to the 15-bit shift register 4 for descrambling The lower third and fourteenth bits DEC <2 and 13> of the fifth and gate 71 to be output and the decoded data DEC [15: 0] output from the ID register data decoding unit 2 are logically multiplied. A sixth end gate 72 which outputs the second bit of the descrambling preset signal (DSC-RS <1>) to the 15-bit shift register 4 for descrambling, and the ID register data decoding unit 2 The least significant bit (DSC-RS <) of the descrambling preset signal by ANDing the highest and lower eleventh and twelfth bits (DEC <10, 11, 15>) of the decoded data DEC [15: 0] output from 0>) The descrambler of the DS DVD, comprising a seventh and gate 73 output to the 15-bit shift register (4). The descramble 15 bit shift register (4) is provided with a reset enable signal (RES-EN) input from the outside, a system clock (SF-CK) input from the outside, and the reset / A descrambling and shifting unit 81 for descrambling and shifting each of the 15-bit descrambling preset signals DSC-RS [-: 14] output from the set signal generator 3, and the The 8-bit signal output from the descrambling and shifting unit 81 and the 8-bit data SDB [7: 0] input through the data bus are exclusively ORed to descramble the output data (DSC-O [0). : 7]) descrambler of the SD DVD, characterized in that it comprises an exclusive logical sum 82. The apparatus of claim 5, wherein the descrambling and shifting unit (81) resets the reset enable signal (RES-EN) that is input from the outside, the system clock (SF-CK) input from the outside, and the fed back data. The least significant bit (DSC-RS <0>) from the 15-bit descramble preset signal (DSC-RS [0:14]) outputted from the set signal generator 3 to descramble the input to the exclusive logic. A first descrambling unit 91 output to the summation unit 82, a reset enable signal RES-EN input from the outside, a system clock SF-CK input from the outside, and the first descrambling unit ( A lower second bit (DSC-RS <1) among a signal output from 91 and a 15-bit descramble preset signal (DSC-RS [0:14]) output from the reset / set signal generator 3; Descrambling &quot;) as an input and outputting to the exclusive logical sum 82 The unit 92, a reset enable signal RES-EN input from the outside, a system clock SF-CK input from the outside, and a signal output from the second descrambling unit 92 and the reset / set The lower third bit (DSC-RS <2>) is descrambled as an input among the 15th bit descramble preset signals (DSC-RS [0:14]) output from the signal generator 3 to perform the exclusive operation. A third descrambling unit 93 output to the logic sum unit 82, a system clock SF-CK input from the outside of the reset enable signal RES-EN input from the outside, and a third descrambling unit. The lower fourth bit (DSC-RS) among the signal output from 93 and the fifteenth descramble preset signal DSC-RS [0:14] output from the reset / set signal generator 3. A fourth descrambling 94 for descrambling &quot; From the reset enable signal RES-EN, the system clock SF-CK input from the outside, the signal output from the fourth descrambling unit 94, and the reset / set signal generator 3; The lower fifth bit (DSC-RS <4>) is descrambled as an input among the 15th bit descramble preset signals (DSC-RS [0:14]) to be output to the exclusive logical sum unit 82. The fifth descrambling unit 95, a reset enable signal RES-EN input from the outside, a system clock SF-CK input from the outside, and a signal output from the fifth descrambling unit 95; The lower sixth bit (DSC-RS <4>) of the fifteenth bit of the descramble preset signal (DSC-RS [0:14]) output from the reset / set signal generator 3 is used as the input. The sixth descrambling unit 96 which outputs the scrambling process to the exclusive logical sum unit 82 and the reset in input from the outside Able signal RES-EN, a system clock SF-CK input from the outside, a signal output from the sixth descrambling unit 96, and a fifteenth bit output from the reset / set signal generator 3; A seventh descrambling unit which descrambles the lower seventh bit (DSC-RS <6>) as an input among the descrambling preset signals DSC-RS [0:14] and outputs the descrambling preset unit 82 to the exclusive logical sum unit 82. (97), a reset enable signal RES-EN input from the outside, a system clock SF-CK input from the outside, a signal output from the seventh descrambling unit 97, and the reset / set signal; The exclusive logic of the 15th bit descramble preset signal (DSC-RS [0:14]) output from the generation unit 3 is descrambled as an input and the exclusive logic is performed. An eighth descrambling part 98 outputted to the summation part 82, a reset enable signal RES-EN input from the outside; The signal output from the system clock SF-CK and the eighth descrambling section 98 and the fifteenth bit of the descramble preset signal DSC output from the reset / set signal generation section 3 A ninth descrambling unit 99 which descrambles the lower ninth bit (DSC-RS <8>) as an input from among RS [0:14]), and a reset enable signal RES-EN input from the outside ) And the system clock SF-CK input from the outside, the signal output from the ninth descrambling section 99 and the fifteen-bit descramble preset signal output from the reset / set signal generator 3. The tenth descrambling unit 100 which descrambles the lower tenth bit (DSC-RS <9>) as an input among the DSC-RS [0:14], and the reset enable signal RES input from the outside. -EN) and a system clock SF-CK input from the outside and a signal output from the tenth descrambling unit 100. And the lower eleventh bit (DSC-RS <10>) from the 15th bit descramble preset signal (DSC-RS [0:14]) output from the reset / set signal generator 3 as an input. From the eleventh descrambling unit 101 for descrambling processing, the reset enable signal RES-EN input from the outside, the system clock SK-CK input from the outside, and the eleventh descrambling unit 101 The lower 12th bit (DSC-RS <11>) among the output signal and the 15th bit descramble preset signal (DSC-RS [0:14]) output from the reset / set signal generator 3. 12th descrambling unit 102 for descrambling as input, a reset enable signal RES-EN input from the outside, a system clock SF-CK input from the outside, and the 12th descrambling unit ( A disk output from the signal 102 and the fifteenth bit output from the reset / set signal generator 3 A third descrambling part 103 which descrambles the lower 13th bit (DSC-RS <12>) as an input among the double preset signals DSC-RS [0:14], and a reset in input from the outside Able signal RES-EN, a system clock SF-CK input from the outside, a signal output from the thirteenth descrambling unit 103, and a fifteenth output from the reset / set signal generator 3 A fourteenth descrambling unit 104 which descrambles the lower fourteenth bit (DSC-RS <13>) as an input from among the descrambling preset signals DSC-RS [0:14] of bits, which is input from an external source. The reset enable signal DSC-RS <13>, the system clock SF-CK input from the outside, the signal output from the fourteenth descrambling unit 104, and the reset / set signal generator 3 The most significant bit (DSC-RS <14>) from the 15th bit descramble preset signal (DSC-RS [0:14]) output from An exclusive OR gate for feeding back to the first descrambling unit 91 by exclusively ORing the signals output from the fifteenth descrambling unit 105 for scrambling and the eleventh and fifteen descrambling units 101, 105. And a descrambler for the SD DVD. The method of claim 6, wherein the first to 15 descrambling parts (91,92,93,94,95,96,97,98,99100,101,102,103,104,105) are output from the reset / set signal generator (3). Inverter 110 for inverting each 15-bit descramble preset signal DSC-RS [0:14], and each 15-bit descramble free output from the reset / set signal generator 3 A first end gate 111 that negatively multiplies a set signal DSC-RS [0:14] and a reset enable signal RES-EN input from the outside, and an output of the inverter 110 and an input from the outside The second and gate 112 negatively multiplying the reset enable signal RES-EN, and the descrambling portions 91, 92, 93, 94, 95, 96 and the exclusive ora gate 106; 97,98,99,100,101,102,103,104 are signals inputted from the first and second end gates 111 and 112, respectively. Force and a descrambler of a SD DVD, characterized in that consisting of the flip-flop 113 as a clock input for a system clock (SF-CK) input from the outside. The exclusive logic summation unit 82 is an 8-bit signal output from the descrambling and shifting unit 81 and 8-bit data input through the database bus (SDB [7: 0]). ), Which is composed of eight exclusive OR gates 121 to 128 for outputting descrambling output data (DSC-O [0: 7]) by exclusive OR. ※ Note: The disclosure is based on the initial application.