KR0139979B1 - 16-Bit Parallel Descrambler for S.D.-ROM Decoder - Google Patents

Abstract

The present invention relates to a 16-bit parallel descrambler of a CD-ROM decoder. By using 16-bit descrambling of the conventional descrambler by one bit, the entire circuit is reduced by reducing unnecessary registers. The present invention relates to a 16-bit parallel descrambler of a CD-ROM decoder capable of speeding up processing.

Description

16-Bit Parallel Descrambler for S.D.-ROM Decoder

1 is a block diagram showing a S.D.-ROM decoder and peripherals.

2 shows a typical scrambling data generation circuit using polynomial [p (x) = X ¹⁵ + X +1].

3 is a block diagram showing a conventional descrambler.

4 is a diagram illustrating a process of deriving a 16-bit parallel descrambling data generation equation according to an embodiment of the present invention.

5 is a block diagram illustrating a 16-bit parallel descrambler of a S.D.-ROM decoder according to an embodiment of the present invention.

FIG. 6 is a detailed diagram of a 16-bit parallel descrambling data generation circuit in a 16-bit parallel descrambler of a S.D.-ROM decoder according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

51: CD-lF Block 52: Sync Detect Block

53: 16-Bit Parallel Descrambling Data Generation Circuit

54: DSCR Block

The present invention relates to a 16-bit parallel descrambler of a CD-ROM (CD-ROM) decoder. The present invention relates to a 16-bit parallel descrambler of a CD-ROM decoder that can simplify a circuit and increase a processing speed by 16 bits of descramble heart.

In synchronous data transmission, in general, random data signals are used by the shift register at the transmitting side in order to avoid losing timing information due to a long period of no conversion point, such as 0 or 1 transmission of data to be transmitted. Many times. This randomized circuit is called a scrambler. The receiving side converts the original data signal by a descrambler that performs the reverse operation. The scrambler divides the transmission data signal into constant polynomials (Po1ynomial), but the descrambler returns the original data signal by multiplying the scrambled data signal into constant polynomials.

Meanwhile, in a compact disk-digital audio (CD-DA) system, an artificial method called scrambling is used to reduce the probability of generating a pattern identical to a sync signal in audio data.

Therefore, in the CD-ROM decoder, since 2340 bytes of scrambling processing except for 12 bytes of the sync part are performed among one block, that is, 2352 bytes of data, the descrambling process of restoring the original signal at the time of reproduction is performed. It is essential.

Hereinafter, the prior art will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a CD-ROM decoder and a peripheral device, and shows a position occupied by a descrambler in a system.

FIG. 2 shows a typical scrambling data generation circuit using polynomial [p (x) = X ¹⁵ + x + 1], where the input data is synchronized to the clock and the XOR (through a scramble register using multiple flip flops). Exclusive OR) shows the process of outputting scrambled data through the gate.

The scramble register is a 15-bit shift register with feedback according to the polynomial [p (x) = X ¹⁵ + x + 1], and the initial value of the scramble register is 000000000000001.

3 is a block diagram showing a conventional descrambler.

As shown in Figures 1 and 3,

The descrambler of the CD-ROM decoder used conventionally,

SPCI (Serial) that receives SIDATA (Serial Input DATA), MCK (Main Clock), and LMSEL (control signals) from a compact disk player (CDP; Compact Disk Player), and makes SIDATA, which is input by 1 bit, into 16-bit parallel data. To Parallel Converter 1) and a CD-IF (CD-Interface) block 31 composed of Data Ordering for determining a CD-data format according to the LMSEL signal, and the CD-IF block 32 described above. A sink detect block 32 which finds a sync signal from the data outputted from the N-th output signal and outputs a sync start, sync detect, and sync end signal;

A descrambling data generation circuit 33 for receiving a clock and generating and outputting descrambling data through a shift register using one XOR gate and a plurality of flip flops;

Parallel to Seeial Converter 1 (PSCI) for converting 16-bit data output from the CD-IF block 31 into serial bits one by one, and the output of the PSCI and the descrambling data generating circuit 33. A two-input XOR gate that receives the output and descrambles the two data, an SPC2 that receives one-bit serial output from the two-input XOR gate and converts it back to 16-bit, and receives the 16-bit output of the SPC2. Descrambling (DSCR) block 34, which consists of LR Left-Right Divider (LR DIV) that separates data into 8 bits of left and write for error correction, and outputs the final descrambled data to RAM. Consists of.

However, the conventional descrambler has a problem in that additional registers are used by separately performing serial and parallel conversion and data ordering in the CD-IF block 31.

In addition, since the descrambling data generation circuit 33 having a 1-bit serial structure outputs the descrambling data to the DSCR block 34 in units of 1 bit, the signal output as 16 bits in the CD-IF block 31 is synchronized with the decoded data. In the text block 32, the sync pattern can be generated as a sync start / detect / end signal, but in the DSCR block 34, descrambling is possible only by switching back to serial data through PSCI. There is a problem, and due to this problem, the DSCR block 34 has a disadvantage in that the descrambled data must be converted from the SPC2 back to 16-bit parallel data.

Accordingly, an object of the present invention is to solve the above-described conventional problem, and enables the execution of the CD-IF block 31 at once, and 16-bit descrambling data output from the descrambling data generating circuit 33. It is intended to provide a 16-bit parallel descrambler of the S.D.-ROM decoder that can be generated in units, thereby simplifying the entire circuit and increasing the processing speed.

As a means for achieving the above object, the configuration of the present invention,

A CD-IF block which simultaneously receives the SIDATA and LMSEL signals inputted by 1 bit and makes 16-bit parallel data and performs data ordering to determine the CD-data format at once;

The sync detect block finds a sync signal from the data output from the CD-IF block and outputs a sync start, sync detect, and sync end signal, a shift register using a plurality of flip flops, and a plurality of flip flops. 16-bit parallel descrambling data generation circuit for generating and outputting 16-bit parallel descrambling data through an XOR gate;

16 2-input KOR gates that descramble two 16-bit data by receiving the 16-bit data output from the CD-IF block and the output of the 16-bit parallel descrambling data generation circuit, and the 16 2 It consists of a DSCR block containing L-RDIV that receives a 16-bit output from the input XOR gate and separates the data into 8 bits of the left write for error correction and outputs the final descrambled data.

With the above configuration, the most preferred embodiment which can be easily carried out by those skilled in the art with reference to the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram illustrating a 16-bit parallel descrambler of a S.D.-ROM decoder according to an embodiment of the present invention.

As shown in FIG. 5, the configuration according to the embodiment of the present invention is

A CD-IF block that simultaneously receives the SIDATA and LMSEL signals inputted from the compact disc player (not shown) at the same time and makes 16-bit parallel data and performs data ordering for determining the CD-data format at once. )and,

A sink detect block 52 which finds a sync signal from the data output from the CD-IF block 51 and outputs a sync start, sync detect, and sync end signal;

A 16-bit parallel descrambling data generation circuit 53 which receives a clock from a compact disc player (not shown) and generates and outputs 16-bit parallel descrambling data through a shift register using a plurality of flip flops and a plurality of XOR gates; ,

16 two-input XOR gates that receive the 16-bit data output from the CD-IF block 51 and the output of the 16-bit parallel descrambling data generation circuit 53 and descramble the two 16-bit data; And L-RDIV for receiving the 16-bit output from the 16-bit XOR gate and separating the data into 8 bits of the left write for error correction and outputting the final descrambled data. DSCR block 54, including.

6 is a detailed diagram of a 16-liter parallel descrambling data generation circuit in a 16-bit parallel descrambler of a S.D.-ROM deloader according to an embodiment of the present invention.

As shown in FIG. 6, the configuration of the 16-bit parallel descrambling data generation circuit according to the embodiment of the present invention is

First and second flip-flops 511 and 512 for receiving data fed back in synchronization with an externally input clock and outputting data held therein;

A first XOR gate 527 that receives the outputs of the first and second flip flops 511 and 512 and performs an exclusive OR;

A third flip-flop 513 that receives the output of the first XOR gate 527 in synchronism with a clock input from the outside and outputs the data therein;

A second XOR gate 528 that receives the outputs of the second and third flip flops 512 and 513 and outputs an exclusive OR;

A fourth flip-flop 514 which receives the output of the second XOR gate 528 in synchronization with a clock input from the outside, and outputs the data which has been held;

A third XOR gate 529 which receives an output of the third and fourth flip flops 513 and 514 and outputs an exclusive OR;

A fifth flip-flop 515 that receives the output of the third XOR gate 529 in synchronization with a clock input from the outside, and outputs data which has been held;

A fourth XOR gate 530 which receives the outputs of the fourth and fifth flip flops 514 and 515 and outputs an exclusive OR;

A sixth flip-flop 516 that receives the output of the fourth XOR gate 530 described above in synchronization with a clock input from the outside and outputs the data which has been held;

A fifth XOR gate 531 which receives the outputs of the fifth and sixth flip flops 515 and 516 and outputs an exclusive OR;

A seventh flip-flop 517 that receives the output of the fifth XOR gate 531 described above in synchronization with a clock input from the outside and outputs the data that the apparatus has;

A sixth XOR gate 532 which receives an output of the sixth and seventh flip-flops 516 and 517 and outputs an exclusive OR;

An eighth flip-flop 518 that receives the output of the sixth XOR gate 532 in synchronization with a clock input from the outside and outputs the data that the apparatus has;

A seventh XOR gate 533 for receiving an output of the seventh and eighth flip flops 517 and 518 and performing an embryonic OR;

A ninth flip-flop 519 which receives the output of the seventh XOR gate 533 in synchronization with a clock input from the outside, and outputs the data which it has;

An eighth XOR gate 534 which receives the outputs of the eighth and ninth flip flops 518 and 519 and outputs an exclusive OR;

A tenth flip-flop 520 for receiving the output of the eighth XOR gate 534 in synchronization with a clock input from the outside and outputting the data;

A ninth XOR gate 535 that receives the outputs of the ninth and tenth flip-flops 519 and 520 and outputs an exclusive OR;

An eleventh flip-flop 521 that receives the output of the ninth XOR gate 535 in synchronization with a clock input from the outside, and outputs the data;

A tenth XOR gate 536 which receives the outputs of the tenth and eleventh flip-flops 520 and 521 and outputs an exclusive OR;

A twelfth flip-flop 522 that receives the output of the tenth BOR gate 536 in synchronization with a clock input from the outside and outputs the data that the apparatus has;

An eleventh XOR gate 537 that receives the outputs of the eleventh and twelfth flip-flops 521 and 522 and performs an exclusive OR;

A thirteenth flip-flop 523 which receives the output of the eleventh XOR gate 537 in synchronization with a clock input from the outside and outputs the data;

A twelfth BOR gate 538 that receives the outputs of the twelfth and thirteenth flip-flops 522 and 523 and outputs an exclusive OR;

A fourteenth flip-flop 524 that receives the output of the twelfth XOR gate 538 in synchronization with a clock input from the outside, and outputs data which has been held;

A thirteenth XOR gate 539 that receives the outputs of the thirteenth and fourteenth flip-flops 523 and 524 and outputs an exclusive OR;

A fifteenth flip-flop 525 which receives the output of the thirteenth XOR gate 539 in synchronization with a clock input from the outside and outputs the data;

A fourteenth BOR gate 540 which receives the outputs of the fourteenth and fifteenth flip flops 524 and 525 and outputs an exclusive OR;

A sixteenth flip-flop 526 which receives the output of the fourteenth BOR gate 540 in synchronization with a clock inputted from the outside and outputs data which has been held;

A fifteenth BOR gate 541 that receives the outputs of the fourteenth and sixteenth flip-flops 524 and 526 and performs an exclusive OR to feedback the second flip-flop 512 to an output;

The sixteenth XOR gate 542 receives the outputs of the thirteenth and fifteenth flip flops 523 and 525 and performs an exclusive OR to feedback the first flip flop 511 to the first flip flop 511.

With the above configuration, the operation according to the embodiment of the present invention is as follows.

Conventional descramblers have latched SIDATA in a 16-bit shift register and then set the input format according to the LMSEL signal. However, in the present invention, the CD-IF block 51 inputs one bit from a compact disc player (not shown). It simultaneously receives the SIBATA and LMSEL signals and performs data ordering to determine the SPC and the CD-data format to make 16-bit parallel data. In the sync detect block 52, a sync signal is found from the data output from the CD-LP block 51, and a sync start, sync detect, and sync end signal are output.

Meanwhile, the 16-bit parallel descrambling data generation circuit 53 having an initial value of 1000000000000001 is a shift register using 16 flip flops and 16 XORs in synchronization with a clock (T = 16t) input from a compact disc player (not shown). 16-bit parallel descrambling data is generated through the gate and 16 bits are output to the DSCR block 54 at a time.

Next, the 16-bit XOR gate in the DSCR block 54 receives the 16-bit data output from the CD-IF block 51 and the output of the 16-bit parallel descrambling data generation circuit 53. LR DIV in the DSCR block 54 described above by descrambling 16-bit data. Output to

And L-R DIV. In the DSCR block 54 described above. The 16-bit output received from the 16-bit XOR gate divides the data into 8 bits of the left write for error correction, and outputs the final descrambled data in RAM.

4 is a diagram illustrating a process of deriving a 16-bit parallel descrambling data generation equation according to an embodiment of the present invention.

As shown in FIG. 4, a 1-bit descrambling data value is placed in a 16-bit shift register to derive a method of generating 16-bit parallel descrambling data in a 16-bit parallel descrambling data generating circuit. Was extracted.

If you attempt to write the nth dscr [1:16] value as dscr ⁽ⁿ⁾ [1:16], the first dscr [1:16], that is, the dscr ⁽¹⁾ [1:16] value is ds15 [1:15] Since the initial value of is 000000000000001, it is 1000000000000001.

The relationship ^between dscr ⁽¹⁾ [1:16] and dscr ⁽²⁾ [1:16] is expressed as follows.

dscr ^(s) [x] = dscr ⁽¹⁾ [x + 1] xor dscr ⁽¹⁾ [x + 2] (Equation-1)

Where 1 ≦ x ≦ 14

dscr ⁽²⁾ [x] = dscr ⁽¹⁾ [x-14] xor dscr ⁽¹⁾ [x-12] (Equation-2)

Where 15 ≤ x ≤ 16

Extending (Equation-1) and (Equation-2) to dscr ⁽ⁿ⁾ [1:16] and dscr ^{(n + 1)} [1:16] to derive the general formula

dscr ^{(n + 1)} [x] = dscr ⁽ⁿ⁾ [x + 1] xor dscr ⁽ⁿ⁾ [x + 2] (expression -3)

Where 1 ≦ X ≦ 14

dscr ^{(n + 1)} [xl = dscr ⁽ⁿ⁾ [x-14] xor dscr ⁽ⁿ⁾ [x-12] (Equation-4)

Where 15 ≤ x ≤ 16

16-bit parallel descrambling data generation circuit is shown in FIG. 6 by Equation-3 and Equation 4, and the clock used here is divided by 16 divisions of the clock used in the existing 1-bit descrambling data generation circuit. use.

For example, when SIDATA, I ₁ , I ₂ ..., I ₃₂ , ... enter, the existing 1-bit descrambling data generation circuit uses the contents of dscr [16] of FIG. 4 and SIDATA. Xorated in bits, I ₁ 1, I ₂ 0, I ₃ 0, I ₄ 0, ......, I ₁₆ 1, I ₁₇ 0, ......, I ₃₀ 1, I ₃₁ 1, I ₃₂ 0.

Since the initial value of the 16-bit parallel descrambling data generation circuit of the present invention is 1000000000000001, the xor result with I ₁ -I ₁₆ is the same as the existing result.

If dscr ⁽¹⁾ [1:16] is used to obtain the value of dscr ⁽²⁾ [1:16] using (Equation-3) and (Equation-4), it is 0000000000000110. Therefore, if dscr ⁽²⁾ [1:16] and I ₁₇ -I ₃₂ xor, the descrambled data I ₁₇ 0, I ₁₈ 0, ......, I ₃₀ 1, I ₃₁ 1, I ₃₂ 0 can be obtained.

The circuit used for inductive extraction, shown at the top of FIG. 4, is another embodiment of a 16-bit parallel descrambling data generation circuit, and the 16-bit parallel descrambling data generation circuit according to an embodiment of the present invention is shown in FIG. The circuit shown is an improvement and the action is the same.

As described above, in the embodiment of the present invention, the area of the circuit is reduced by reducing 32 registers than in the conventional descrambler, and the 16-bit parallel descrambling data generation circuit uses the 16-division clock of the existing clock, thereby providing SIDATA. If the input speed of the device is increased, a 16-bit parallel descrambler of a CD-ROM decoder capable of high speed processing can be provided.

This effect of this invention can be used for all CD-ROM decoders.

Claims (4)

A CD-IF block which simultaneously receives the SIDATA and LMSEL signals inputted by 1 bit and makes 16-bit parallel data and performs data ordering for determining the CD-data format at once, and the output from the CO-IF block. 16-bit parallel descrambling through a sink detect block that finds the sync signal in the data and outputs sync start, sync detect, and sink end signals, a shift register using multiple flip-flops with a clock input, and multiple XOR gates 16-bit parallel descrambling data generation circuit for generating and outputting data, 16-bit data output from the CD-IF block and output of the 16-bit parallel descrambling data generation circuit. 16-bit XOR gate and a 16-bit output from said 16-bit XOR gate. L-R DIV that receives the data and separates the data into 8 bits of the left write for error correction and outputs the final descrambled data. 16-bit parallel descrambler of the CD-ROM decoder, characterized in that consisting of a DSCR block. The first and second flip-flops 511 and 512 according to claim 1, wherein the 16-bit parallel descrambling data generating circuit receives data fed back in synchronization with an externally input clock and outputs the data. ), A first XOR gate 527 that receives an output of the first and second flip-flops 511 and 512 and performs an exclusive OR, and outputs the first XOR gate in synchronization with an external clock. A third flip-flop 513 that receives the output of the gate 527 and outputs the data that it has, and the outputs of the second and third flip-flops 512 and 513 that receive the output and perform an exclusive OR A second flip-flop 514 for receiving the output of the second XOR gate 528 described above in synchronization with a clock, the second XOR gate 528 and an externally-injected clock, and outputting the data; The output of the third and fourth flip flops 513 and 514 is input to perform an exclusive OR. The third XOR gate 529 to be outputted, the fifth flip-flop 515 to receive the output of the third XOR gate 529 described above in synchronization with a clock input from the outside, and to output the data held therein; A fourth XOR gate 530 that receives the outputs of the fourth and fifth flip flops 514 and 515 and performs an exclusive OR, and outputs the fourth XOR gate 530 in synchronization with an externally input clock. The fifth flip-flop 516 that receives the output of < RTI ID = 0.0 >), < / RTI > and the fifth XOR that receives the output of the fifth and sixth flip-flops 515 and 516 and performs an exclusive OR on the output. A seventh flip-flop 517 that receives the output of the fifth XOR gate 531 described above in synchronization with a gate 531 and a clock input from the outside, and outputs the data; A sixth XOR gate 532 that receives the output of the seven flip flops 516 and 517 and outputs an exclusive OR. ), An eighth flip-flop 518 that receives the output of the sixth XOR gate 532 in synchronization with an externally input clock, and outputs the data, and the seventh and eighth flip-flops described above. A seventh XOR gate 533 for receiving an output of (517, 518) and outputting an exclusive OR, and an output of the seventh XOR gate 533 in synchronization with an external clock. An eighth flip-flop 519 that outputs data, an eighth XOR gate 534 that receives the outputs of the eighth and ninth flip-flops 518 and 519 and outputs an exclusive OR; The tenth flip-flop 520 for receiving the output of the eighth XOR gate 534 and outputting the data in synchronization with the clock, and the ninth and tenth flip-flops 519 and 520. A ninth XOR gate 535 that receives an output and performs an exclusive OR, and outputs the clock; In synchronization, the output of the ninth XOR gate 535 is input, and the eleventh flip-flop 521 for outputting the data, and the outputs of the tenth and eleventh flip-flops 520 and 521 are input. A twelfth flip-flop that receives the output of the tenth XOR gate 536 and the output of the tenth XOR gate 536 in synchronization with a clock input from the outside and outputs the data, 522, an eleventh XOR gate 537 that receives the outputs of the eleventh and twelfth flop flops 521 and 522 and performs an exclusive OR, and outputs the same; The output of the XOR gate 537 is received, the 13th flip-flop 523 for outputting the data, and the outputs of the 12th and 13th flip-flops 522 and 523 are received, and the output is performed by performing an exclusive OR. The twelfth XOR gate 538 and a clock input from an external source The output of the twelfth XOR gate 538 is input, and the fourteenth flip-flop 524 for outputting the data, and the outputs of the thirteenth and fourteenth flip-flops 523 and 524 are received. A thirteenth XOR gate 539 to be outputted, a fifteenth flip-flop 525 to receive the output of the thirteenth XOR gate 539 in synchronization with a clock input from the outside, and to output the data; A fourteenth XOR gate 540 that receives the outputs of the fourteenth and fifteenth flip-flops 524 and 525 and outputs an exclusive OR, and the fourteenth XOR gate 540 in synchronization with a clock input from the outside. 16th flip-flop 526 that receives the output of the < RTI ID = 0.0 >), < / RTI > and the output of the 14th, 16th, 16th flip-flops 524, 526. A fifteenth XOR gate 541 for feedback output to the flop 512, and the thirteenth and fifteenth flips A 16-bit parallel decode of a CD-ROM decoder comprising a sixteenth XOR gate 542 which receives the outputs of the robs 523 and 525 and performs an exclusive OR and feedbacks the feedback to the first flip-flop 511. Scrambler. The 16-bit parallel descrambler of a CD-ROM decoder according to claim 1 or 2, wherein the 16-bit parallel descrambling data generated in the 16-bit parallel descrambling data generating circuit is derived from the following equation. dscr ^{(n + 1)} [x] = dscr ⁽ⁿ⁾ [x + 1] xor dscr ⁽ⁿ⁾ [x + 2] Where 1 ≦ X ≦ 14 dscr ^{(n + 1)} [xl = dscr ⁽ⁿ⁾ [x-14] xor dscr ⁽ⁿ⁾ [x-12] Where 15 ≤ x ≤ 16 The 16-bit parallel descrambler of the CD-ROM decoder according to claim 2, wherein the initial value of the 16-bit parallel descrambling data generation circuit is 1000000000000001.