KR930005438B1 - Parallel processing discrambling circuit of decoding system for cdp - Google Patents

Abstract

The circuit reconstructs scrambled data into original data by descrambling it by word or byte unit according to the sync. pattern of the data to be reproduced. The circuit includes a selecting signal input port (SEL) for receiving selecting signal, an input port (INT) of initial descramble data for receiving initial descramble data (IR0-IR14) of constant 15 bit, a descramble data storage section (20) for latching/outputting next 15 bit descramble data as descramble data (DR0-DR14), a basic descramble data generator (30) for generating basic descramble data (EX0-EX15) of 16 bit, and a descramble processor (50) for reconstructing original data.

Description

Parallel Descramble Circuit of Compact Disc Decoding System

1 is a recording data format diagram of a CD-ROM.

2 is a system configuration to which the present invention is applied.

3 is a block diagram of a descramble circuit according to the present invention.

4 is a detailed circuit diagram of one embodiment of the basic descramble data generator 30 of FIG. 3 according to the present invention.

5 is a detailed circuit diagram of an embodiment of the next descramble data generator 40 of FIG. 3 according to the present invention.

6 is a detailed circuit diagram of an embodiment of the descramble processing unit 50 of FIG. 3 according to the present invention.

* Explanation of symbols for main parts of the drawings

10: clock signal selection unit 20: descramble data storage unit

30: basic descramble data generator 40: next descramble data generator

50: descramble processing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing descramble circuit of a compact disk (CD) type decoding system, and more particularly to a CD type decoding system for parallel processing of playback data. The present invention relates to a descrambling circuit for selectively descrambled scrambled data to be reproduced and inputted in word or byte units and restoring the original data according to detection of a sync pattern of each block.

Currently, a CD system using a CD, which is a medium capable of storing a large amount of digital information and reproducing the stored information by optical reproduction, is used in various information reproducing apparatuses.

CD-ROM (ROM), CD-I (Interactive), etc. are used by the CD method, and data encoded for recording is recorded in a certain format according to the CD method signal specification.

For example, a CD-ROM is divided into a plurality of blocks, and each block is recorded with 2352 bytes per block in the format shown in FIG. In FIG. 1, the sync pattern of 12 bytes is data for synchronization of each block. The first and last 1 bytes are defined as "00" as hexadecimal values, and the remaining 10 bytes are defined as "FF". As a result, data recorded in the format shown in FIG. 1 can be reproduced and decoded to detect the synchronization pattern of the predetermined format as described above.

In addition, in the current CD-ROM and CD-I, etc., when recording data, the original data is scrambled and recorded in a predetermined format. This prevents the recording data from becoming the same as the sync pattern as described above, and generates a CD during playback. This is to reduce the effects of errors due to contamination. Therefore, when the data recorded as described above is reproduced and decoded, it is descrambled in reverse with that of the scramble according to the CD-type signal definition, and used to restore the original data.

The descramble circuit of the CD type decoding system as described above is described in detail in 1990 patent application 6262 of the same applicant as the present applicant. In the above-mentioned patent application No. 6264, the scrambled data, which is input after being picked up and reproduced and serially input, is converted into parallel data in word units, descrambled in word units, and stored in memory in byte units. This allows computers to freely access the memory at any time to speed up processing.

On the other hand, when the data recorded as described above is descrambled in word units as in the previously filed method, the serial input data is converted into parallel data in word units, and then the format as shown in FIG. The synchronous pattern is detected and the data is descrambled in units of words in accordance with the synchronization of each block to restore the original data.

At this time, when converting serial data into parallel data in word units, the sync pattern is also converted into word units. That is, the synchronization pattern as shown in FIG. 1 described above is "OOFF, FFFF,... … , FFFF, FFOO ”in parallel. At this time, invalid data due to an error generated during reproduction processing of the signal picked up from the CD is for example “XXOO, FFFF,... … , FFFF, OOXX ”(where XX represents invalid data) is inserted into the CD-based decoding system by inserting a synchronization pattern, which may result in conversion of parallel data in word units with invalid data. . In the above case, since the first one byte is invalid, the unit of bytes, that is, “OO, FF,... … FF, OO ”may be used to detect the sync pattern and descramble the data of the parallel unit in the unit of bytes so that accurate data can be restored.

Therefore, in the descramble circuit of the conventional CD decoding system, there is a problem in that original data cannot be restored when invalid data appears in the word unit sync pattern by descramble by word unit.

Accordingly, an object of the present invention is to provide a descramble circuit of a CD-type decoding system that descrambles playback data scrambled in a predetermined format by parallel processing, thereby detecting synchronization patterns according to the type of playback data input after playback processing. Accordingly, the present invention provides a descramble circuit that can selectively restore word data or byte units to accurately restore original data.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a system configuration diagram to which the present invention is applied, and a CD system signal processing unit 1 for reproducing a signal picked up from a CD and outputting serial reproduction data, and shifting the serial reproduction data. Serial-to-parallel (S / P) conversion unit 4 for converting into parallel data in word units, and a sync pattern detection unit 5 for detecting a synchronization pattern from the parallel-converted data. And a descrambler circuit 6 which selectively descrambles the parallel-converted data in byte units and word units and restores the original data in accordance with the sync pattern detection by the sync pattern detection unit 5. A coder 2 and a memory section 3 for storing the restored data.

In the configuration of FIG. 2, a CD-DSP (Digital Signal Processor) chip is typically used for the CD signal processing unit 1, and reproduces the signal picked up from the CD to output digital serial reproduction data.

The outputted serial reproduction data is converted into parallel reproduction data in word units by the S / P conversion section 4, and the reason for conversion into parallel reproduction data is as described above.

Then, the sync pattern detection unit 5 detects a sync pattern from the parallel-converted reproduction data, and initializes the descramble circuit 6 when the sync pattern is detected. The initialization outputs a load signal every time the first sync pattern is detected for every block of reproduction data to load initial descramble data into the descramble circuit 6, and detects the type of sync pattern, that is, the sync pattern. The descramble circuit 6 descrambles the word unit or the byte unit by the selection signal according to the unit.

Accordingly, the descramble circuit 6 loads initial descramble data by the load signal and starts to descramble input reproduction data, and then scrambles the next descramble from the initial descramble data cyclically by a predetermined algorithm. Data is generated and descrambled in units of words or bytes in accordance with the selection signal.

At this time, the initial descramble data is defined by 15-bit “000000000000001”, which is in accordance with the CD system signal specification, and is data stored in a predetermined storage unit. In addition, the algorithm for generating the next descrambled data from the initial descrambled data also follows the CD method signal specification.

Data descrambled as described above and restored to the original data is stored in the memory unit 3 in units of bytes so that a computer can access it.

When the descrambling of the reproduction data for one reproduction data block made as described in FIG. 1 is completed, the synchronization pattern detection unit 5 detects the synchronization pattern of the next block to reinitialize the descramble circuit 6. Repeat the same descrambling process.

Fig. 3 is a block diagram of a descramble circuit according to the present invention, wherein reproduction data input for inputting scrambled reproduction data (PD0-PD15), which is picked up from a CD, reproduced, and then converted into word-by-word parallel data; A selection signal input terminal SEL for inputting a selection signal for selecting a descrambling process in units of words and bytes in accordance with the synchronization pattern detection form of the reproduction data PD0-PD15; A first clock signal input terminal CK1 for inputting a first clock signal having a word unit of data PD0-PD15, and a second clock signal having a byte unit of the reproduction data PD0-PD15; A second clock signal input terminal CK2 for input, a clock signal selector 10 for selecting and outputting the first clock signal and the second clock signal according to the selection signal, and a predetermined 15-bit initial value Descramble data Initial descramble data input terminal INT for inputting (IR0-IR14) and load signal input terminal for inputting a load signal generated each time a sync pattern is detected for each block of the reproduction data PD0-PD15. LD and the initial descrambled data IR0-IR14 are loaded according to the load signal to output the first 15-bit descrambled data DR0-DR14, and then the clock signal selector 10 A descramble data storage unit 20 for latching the next 15 bits of descrambled data NR0-NR14 according to the clock signal to be selectively output, and outputting the descrambled data DR0-DR14 to the descrambled data DR0-DR14; A basic descramble data generator 30 for generating 16-bit basic descrambled data EX0-EX15 by a predetermined logical combination of the data DR0-DR14, and the upper 7 bits of the descrambled data DR0-DR14. Data (DR8-DR14) and the group Next, the descramble data (EX0-EX15) are inputted to correspond to each other and are selected by the selection signal to generate the next 15 bits of descramble data (NR0-NR14) and provide them to the descramble data storage unit 20. The descramble data generator 40 and the reproduced data PD0-PD15 of the reproduced data input terminal PD are stored in the descrambled data DR0-DR14 of the descrambled data storage unit 20 and the basic descrambled data. The exclusive OR is made to correspond to the basic descrambled data EX15 of the most significant bit of the data generator 30, respectively, so that the word-based recovery data DG0-DG15 and the byte-based recovery data DG0-DG7 are selected by the selection signal. It consists of a descramble processing unit 50 to selectively restore.

The configuration of FIG. 3 is a configuration of the descramble circuit corresponding to the descramble circuit 6 of FIG. In addition, the first and second clock signals may be generated by a predetermined division and logical combination of the system clock signal or by using a clock generation circuit.

4 is a detailed circuit diagram of an embodiment of the basic descramble data generation unit 30 of FIG. 3 according to the present invention, and is the highest of 15 bits of descramble data DR0-DR14 of the descramble data storage unit 20. FIG. Input 13-bit data (DR1-DR13) excluding the bit data DR14 and the least significant bit data DR0 into one input terminal, and input the next higher bit data DR2-DR14 into the type-power terminal. Exclusive OR gates 61-73 for inputting each corresponding input and performing exclusive OR to generate basic descrambled data (EX0-EX12) of the lower 13 bits, and the lower 2 bits of the descrambled data (DR0-DR14). Exclusive OR of the data (DR0-DR1) and the most significant bit of the primary descrambled data (EX15) to generate the exclusive oragate 76, and the most significant bit of the descrambled data (DR0-DR14) (DR14). ) And the basic disk The exclusive oracle 74 which generates the exclusive descrambled data EX13 of the upper third bit by exclusively ORing the block data EX15 and the least significant bit of the descrambled data DR0-DR14. ) And an exclusive oracle 75 which generates an exclusive second OR of the lower third bit data DR2 to generate the basic descramble data EX14 of the upper second bit.

FIG. 5 is a detailed circuit diagram of an embodiment of the next descramble data generator 40 of FIG. 3 according to the present invention, wherein the 16-bit basic descramble data EX0-EX5 of the basic descramble data generator 20 is shown. The lower 15 bits of data EX0-EX14 are inputted corresponding to the first to fifteenth input terminals I0A-I14A, respectively, and the 15-bit descrambled data DR0-DR14 of the descrambled data storage unit 20 are input. The first '-15th' input of the most significant bit data EX15 and the least significant 7 bit data EX1-EX6 of the upper 7 bits of data DR8-DR14 and the basic descramble data EX0-EX15. Input data EX0 of the first to fifteenth input terminals I0A-I14A are inputted correspondingly to the terminals I0B-I14B, respectively, during word unit descramble processing by the selection signal of the selection signal input terminal SEL. -EX14) is output to the next 15 bits of descrambled data (DR0-DR14), and when descrambled by byte A multiplexer for selectively outputting the input data (DR8-DR14, EX15, EX0-EX6) of the first 'to the fifteenth input terminals (I0B-I14B) to the next descrambled data (NR0-NR14) of 15 bits. It consists of.

FIG. 6 is a detailed circuit diagram of an embodiment of the descramble processing unit 50 of FIG. 3 according to the present invention. The reproduction data PD0-PD15 of the reproduction data input terminal PD are respectively input to the one input terminal. Input the descrambled data DR0-DR14 of the descrambled data storage unit 20 and the basic descrambled data EX15 of the most significant bit of the basic descrambled data generation unit 30 to the type force terminal, respectively. Exclusive OR gates 77-92 for exclusively ORing the inputs to the terminals and restoring the data to 16 bits of restoration data (DG0-DG15), and the exclusion signals are selected by the selection signal of the selection signal input terminal SEL. It is composed of a tri-state buffer 93-100 that controls the output of the high-order 8-bit recovery data DG8-DG15 output from the sheave ogate 77-84.

Hereinafter, a detailed description will be given with reference to FIGS. 3 to 6 attached to an operation example of the present invention.

First, as shown in FIG. 2, a synchronization pattern is detected from 16-bit scrambled reproduction data PD0-PD15 picked up and reproduced from CD and converted into parallel data in units of words, and the load signal input terminal of FIG. When the load signal is input to the LD, the descramble data storage unit 20 loads and stores the 15-bit initial descramble data IN0-IN14 of the initial descramble data input terminal INT. The data value of the initial descramble data IN0-IN14 is as described above.

The stored 15-bit initial descrambled data IN0-IN14 are output as 15-bit descrambled data DR0-DR14 and input to the basic descrambled data generator 30 configured as shown in FIG. 16-bit basic descramble data (EX0-EX15) is generated. If the 16-bit data is all valid data in the reproduction data PD0-PD15, that is, if the selection signal of the selection signal input terminal SEL is input as a logic " 1 " In the descramble processing unit 50 configured as shown in FIG. 6, the most significant bit data EX15 of the descrambling data DR0-DR14 and the basic descramble data EX0-EX15 is reproduced (PD0-PD15). ) And descramble the exclusive ORs corresponding to Accordingly, as shown in FIG. 2, the 16-bit recovery data DG0-DG15 to be stored in the memory unit is output.

On the other hand, if the selection signal is input with a logic " 0 " for selecting the byte unit processing, only the lower 8 bits of the reproduction data PD0-PD7 of the input reproduction data PD0-PD15 are valid data. Only the 8-bit restoring data DG0-DG7 descrambled by the exclusive OR of the lower 8-bit data DR0-DR7 of the DR0-DR14 becomes the restoring data to be stored in the memory unit.

In this case, the next descramble data generation unit 40 configured as shown in FIG. 5 has a 15-bit next decode for the next reproduction data PD0-PD15 to be processed next by selecting word units or byte units according to the selection signal. The scrambled data NR0-NR14 is generated and provided to the descrambled data storage 20.

Accordingly, after the first regeneration data of one block is descrambled by the initial descramble data IR0-IR14, the descramble data storage unit 20 descrambles the subsequent regeneration data PD0-PD15. The next descramble data NR0 to NR14 for the second latch signal is latched by the first clock signal or the second clock signal which is selectively output according to the selection signal by the clock signal selection unit 10.

The descrambled data storage 20 outputs the descrambled data NR0-NR15 as the descrambled data DR0-DR14 after the latching to descramble the playback data PD0-PD15 which is continuously input. It can be processed. Therefore, after the descramble processing of the reproduction data (PD0-PD15) inputted at the beginning of each block in word units or byte units according to the selection signal, the next descrambled data (PD0-PD15) from the following is described as described above. The occurrence of (NR0-NR14) descrambles word units or byte units and restores them.

Further, the above-described process is repeated for the next playback data PD0-PD15 that is continuously played back until the next load signal is input to descramble the playback data for one block.

At this time, if the sync pattern for the next block is detected, the above-described process is repeated.

Therefore, depending on the sync pattern detection pattern of the reproduction data, the data is selectively descrambled in units of words or bytes to restore the data before being scrambled regardless of the type of the reproduction data.

As described above, the present invention selectively descrambles the word unit or the byte unit according to the detection of the synchronization pattern of the reproduction data input after the reproduction processing, so that even if invalid data is inserted into the synchronization pattern of the reproduction data, the circuit is not modified. As a descramble circuit, there is an advantage in that the original data can be restored accurately.

Claims (1)

In a descramble circuit of a compact disc type decoding system that descrambles compact disc type reproduced data by parallel processing, the disc data is picked up from the compact disc and reproduced and converted into word-level parallel data. Descramble processing by word unit and byte unit according to the reproduction data input terminal PD for inputting the scrambled reproduction data PD0-PD15 and the sync pattern detection for each block of the reproduction data PD0-PD15. A selection signal input terminal SEL for inputting a selection signal for selecting a first signal; a first clock signal input terminal CK1 for inputting a first clock signal in word units of the reproduction data PD0-PD15; And a second clock signal input terminal CK2 for inputting a second clock signal on a byte basis of the playback data PD0-PD15 and the selection signal. The clock signal selector 10 for selecting and outputting the first clock signal and the second clock signal, and an initial descramble data input terminal for inputting a predetermined value of 15-bit initial descramble data IR0-IR14. INT, a load signal input terminal LD for inputting a load signal generated each time a sync pattern is detected for each block of the reproduction data PD0-PD15, and the initial descramble data IR0 by the load signal. -IR14) is loaded to output the first 15-bit descrambled data DR0-DR14, and then the next 15-bit descrambled data NR0- is selected by the clock signal selected and output by the clock signal selector 10. A 16-bit basic descrambled data EX0 is obtained by latching NR14 and outputting the descrambled data storage unit 20 for outputting the descrambled data DR0-DR14 and the descrambled data DR0-DR14. Occurs -EX15) Inputs the basic descramble data generation unit 30, the upper 7 bits of the descrambled data DR0-DR14, and the basic descrambled data EX-EX15 correspondingly. A next descramble data generator 40 for generating the next descrambled data NR0-NR14 of 15 bits selected by the selection signal and providing the descrambled data storage section 20 to the descrambled data storage section 20; The reproduction data PD0-PD15 of the PD is stored in the descrambled data DR0-DR14 of the descrambled data storage unit 20 and the basic descrambled data of the most significant bit of the basic descrambled data generator 30. And a descramble processing unit 50 which performs an exclusive logical OR corresponding to each of EX15) and selectively recovers the word-based restoration data DG0-DG15 and the byte-based restoration data DG0-DG7 by the selection signal. Ugh A parallel processing descramble circuit of a compact disc type decoding system.

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