JPH0850562A - Monitoring circuit for memory - Google Patents

Abstract

PURPOSE:To properly monitor a memory even at the time of a fault to fix memory contents at ALL'0' or ALL'1' by performing error processing coding after the scramble of input data and writing the data in the memory. CONSTITUTION:This circuit is composed of a RAM 1, parity generating circuit 2, parity check circuit 3, scrambler 4, descrambler 5, write control circuit 6, differentiation circuit 7, read control circuit 8 and same code detecting circuit 9. After scramble processing of the input data is performed, a parity bit is added to those data and they are written in the RAM 1. On the read side, descramble processing of the data from which the parity bit is removed is performed, those data are restored into the original data, and a parity check and the same code detection of the read data is performed. Thus, since the data are scrambled on the write side, the fault to fix the RAM 1 to ALL'0' or ALL'1' can be decided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory monitoring circuit, and more particularly, to a memory monitoring circuit for performing error processing coding on input data, writing the same in a memory, and performing error processing decoding on the reading side. Is ALL "0", ALL
The present invention relates to a memory monitoring circuit capable of correctly monitoring a memory even when a failure is fixed at "1".

As the functionality and capacity of the system have increased, the amount of memory used in communication devices has increased, and the effect of memory failure on the system has become enormous. Therefore, the function of monitoring memory failures is becoming more important.

[0003]

2. Description of the Related Art FIG. 7 shows a conventional memory monitoring circuit. In FIG. 7, 1 is a random access memory (RA
M), 2 is a parity generation circuit, 3 is a parity check circuit, 6 is a write control circuit, and 8 is a read control circuit.

In the configuration of FIG. 7, a parity operation is performed on n-bit input data, a 1-bit parity bit is added and written to the RAM, and a parity operation is performed on the n-bit data bit read from the RAM. A bit is generated and compared with the parity bit read from the RAM to perform a parity check. And
If both parity bits match, it is determined that the memory is normal, and if both parity bits do not match, it is determined that the memory has a failure.

[0005]

A method of generating input data in time series is, for example, ALL at idle.
There is a method of generating "0" or ALL "1" and generating data in burst only at a significant time. In such a case,
Even if a failure occurs in which the memory content is fixed to ALL "0" or ALL "1", the failure of the memory cannot be detected during idle, and the failure of the memory occurs only during the time when significant burst data is generated. No detection can be done.

Generally, in order to prevent erroneous judgment due to noise or the like, it is judged that a failure has occurred only after a state in which the failure has continued for a certain period of time (protection time) has continued. Therefore, failure detection cannot be performed if the time during which significant burst-like data is generated is shorter than the protection time.

An object of the present invention is to provide a memory monitoring circuit capable of correctly monitoring the memory even in the event of a failure in which the memory content is fixed at ALL "0" or ALL "1" in order to address such a problem. .

[0008]

FIG. 1 shows the principle of the present invention. In FIG. 1, 1 is a RAM, 2 is a parity generation circuit, 3 is a parity check circuit, 4 is a scrambler, 5
Is a descrambler, 6 is a write control circuit, 7 is a differentiation circuit,
Reference numeral 8 is a read control circuit, and 9 is an identical code detection circuit.

The structure of FIG. 1 is characterized in that a scrambling process is applied to the input data and then a parity bit is added to the RAM.
On the read side, the data excluding the parity bit is descrambled to restore the original data, and the read data is subjected to the same code detection as the parity check.

FIG. 3 shows the second principle of the present invention. FIG.
1, 1 is a RAM, 2 is a parity generation circuit, 3 is a parity check circuit, 4 is a scrambler, 5 is a descrambler, 6 is a write control circuit, 7 is a differentiating circuit, 8 is a read control circuit, and 9 is the same symbol. It is a detection circuit.

The configuration of FIG. 3 is obtained by reversing the order of the parity calculation and the scramble / descramble processing in the configuration of FIG. FIG. 4 shows the third principle of the present invention.

In FIG. 4, 1 is a RAM, 2 is a first parity generation circuit, 2a is a second parity generation circuit, 3 is a first parity check circuit, 3a is a second parity check circuit, and 4 is a scramble. Bra, 5 is descrambler,
6 is a write control circuit, 7 is a differentiation circuit, 8 is a read control circuit,
Reference numeral 9 is an identical code detection circuit.

In the configuration of FIG. 4, a parity bit is generated and written by the second parity generation circuit to the input data before scrambling in the configuration of FIG. 1, and the second parity check circuit generates the second parity. The feature is that the parity check is performed on the descrambled data using the parity bit generated by the generation circuit.

FIG. 5 shows the fourth principle of the present invention. Figure 5
, 1 is RAM, 2 is the first parity generation circuit,
2a is a second parity generation circuit, 3 is a first parity check circuit, 3a is a second parity check circuit, 4 is a scrambler, 5 is a descrambler, 6 is a write control circuit, 7 is a differentiating circuit, 8 Is a read control circuit, and 9 is an identical code detection circuit.

In the configuration of FIG. 5, in the configuration of FIG. 1, the write side scrambles the input data after adding the parity bit to the input data by the second parity generation circuit, and the read side by the second parity check circuit. The feature is that a parity check is performed on the scrambled data.

[0016]

With the configuration shown in FIGS. 1 and 3, since scrambling is performed on the write side, ALL "0" or A is set at idle.
Even if LL "1" occurs, "0" and "1" are always mixed and written. Therefore, unless there is a failure in which the RAM is fixed to ALL "0" or ALL "1", the read side does not become ALL "0" or ALL "1". Therefore, if the same code detection circuit is ALL "0" or ALL
When "1" is detected, RAM is ALL "0" or A
It can be determined that the failure fixed to LL "1" is causing. Moreover, when the RAM causes the above-mentioned failure, the same code is detected even during the idle time and when the significant data is generated, so that the failure time is always detected even when the protection time is set for the failure judgment. Can be detected.

In the configuration shown in FIGS. 4 and 5, the RAM is A
In addition to the fault fixed to LL "0" or ALL "1", if the second parity check circuit gives an alarm when the first parity check circuit does not give an alarm,
It can be determined that the scrambler or descrambler is out of order.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a time chart on the writing side of the configuration of FIG. Input data is sent in an n-bit parallel format in synchronization with a parallel clock. The parallel data is scrambled, but since the order of writing and reading is not fixed in the RAM, the scramble must be performed for each word as a storage unit. Therefore, the scrambler is first reset by the signal obtained by differentiating the parallel clock and then scrambled. The scrambled data is output from the scrambler with a delay of one parallel clock. At the same time, since a parity bit is added, a write enable signal is issued from the write control circuit at this timing to write it in the RAM.
Although a time chart on the reading side is not shown in the figure, the read enable signal output from the read control circuit causes (n
+1) -bit data is read out, a parity check is performed using all (n + 1) -bits, and this (n +
1) The same code is detected for bits. The n bits excluding the parity bit are led to a descrambler, and the descrambler is once reset by a signal obtained by differentiating the parallel clock, and then descrambled to be output.

In FIG. 2, it is explained that the scrambler / descrambler is reset by the signal obtained by differentiating the parallel clock and then the input data / read data is scrambled / descrambled. In order to secure a margin, it is preferable that the clock for generating the differential signal has a phase ahead of the parallel clock for scrambling / descramble.

FIG. 6 shows an embodiment of the present invention. The configuration of FIG. 6 is based on the principle of the present invention shown in FIG. 1, 1 is a RAM, 2 is a parity generation circuit, and 3 is a parity check circuit. Reference numeral 41 is a first pseudo random pattern generation circuit, and 42 is a first exclusive OR circuit, which constitutes a scrambler. Further, 51 is a second pseudo random pattern generation circuit, and 52 is a second exclusive logic circuit, which constitutes a descrambler. Further, 6 is a write control circuit, 7 is a differentiating circuit, 8 is a read control circuit, and 9 is an identical code detection circuit.

Although a specific configuration of the differentiating circuit and the same code detecting circuit is not shown due to space limitations, it is a simple circuit and will be described below in the text. The differentiating circuit is composed of a data flip-flop (D-FF) and a logical product circuit.
A parallel clock is supplied to the data input terminal of F, and D-FF
Of the AND circuit is connected to one input terminal of the AND circuit, the other input terminal of the AND circuit is connected to the inverted output terminal of the D-FF, and the serial clock is supplied to the clock terminal of the D-FF. Then, a differential signal having a length equal to the period of the serial clock at the rising edge of the parallel clock can be obtained.

On the other hand, the same code detection circuit uses the data read from the RAM as (n +) of the first AND circuit.
1) is supplied to the input terminal, and on the other hand, the read data is inverted and supplied to the (n + 1) input terminal of the second AND circuit, and the outputs of both AND circuits are ORed. To configure. That is, the second AND circuit outputs "1" for ALL "0", the first AND circuit outputs "1" for ALL "1", and "0" is output. When "1" is mixed, neither AND circuit outputs "1", so that the same code can be detected.

Since the other circuits are realized by a general-purpose IC and are easily available, detailed description of the configuration will be omitted. Here, an embodiment corresponding to the principle of the present invention has been described. Embodiments can be constructed in exactly the same manner for the second to fourth principles, and thus their description will be omitted.

In the above, RA is used as the memory.
An example has been described in which M is added and parity bits are added and scrambled on the write side, and parity check, descrambling, and identical code detection are performed on the read side. However, the memory to which this idea can be applied is not limited to RAM. Absent.

In the read-only memory (ROM), if parity bits are added and scrambled data is written, and the same code detection and descrambling as the parity check are performed at the time of reading, the same effect as described above is obtained in the ROM. It goes without saying that you can get

Further, in the above description, the parity check method is adopted as the error detection method, but various error detection codes and error correction codes can be adopted. In this sense, in general, the parity generating circuit should be an error processing coding circuit and the parity check circuit should be an error processing decoding circuit.

[0027]

As described above, according to the present invention, the RAM
It is possible to realize a circuit that can reliably detect even if a failure is fixed at ALL "0" or ALL "1".
Further, a failure of the scrambler / descrambler added for that purpose cannot be specified, but a circuit capable of detection is realized. Moreover, the idea of the present invention can be applied not only to RAM but also to ROM.

[Brief description of drawings]

FIG. 1 is a principle of the present invention.

FIG. 2 is a time chart on the writing side of the configuration of FIG.

FIG. 3 is a second principle of the present invention.

FIG. 4 is a third principle of the present invention.

FIG. 5 is a fourth principle of the present invention.

FIG. 6 is an example of the present invention.

FIG. 7: Conventional memory monitoring circuit

[Explanation of symbols]

 1 random access memory (RAM) 2 parity generation circuit 3 parity check circuit 4 scrambler 5 descrambler 6 write control circuit 7 differentiating circuit 8 read control circuit 9 same code detection circuit

Claims (5)

[Claims] 1. The input data is scrambled and then subjected to error processing coding to write the data into a memory, and when the written data is read out, the data read out from the memory is subjected to the error processing decoding. At the same time, the same code detection is performed on the read data, and further, descramble is performed on the data excluding the error processing bits in the read data. 2. The input data is scrambled after being subjected to error processing coding and written into the memory, and when the written data is read out, the same code is detected with respect to the data read out from the memory, and A memory monitoring circuit, wherein the read data is descrambled, and the descrambled data is error-processed and decoded. 3. The input data is scrambled, then error-processed and coded, and the first error-processed bit is added to the input data. When data is added to the memory and the written data is read out, error processing decoding is performed on the scrambled data to which the first error processing bit is added, and the scrambled data is added to the scrambled data. Identical code detection is performed on data to which the first error processing bit is added, descrambling is performed on scrambled data, and error processing is performed by adding a second error processing bit to the descrambled data. A memory monitoring circuit characterized by performing decoding. 4. The data to which error processing coding is applied to the input data and the second error processing bit is added is scrambled, and the scrambled data is subjected to error processing coding to add the first error processing bit. When the written data is read and the written data is read, the error correction decoding is performed on the data read from the memory, the same code is detected for the data read from the memory, and the data is read from the memory. The memory monitoring circuit is characterized in that descramble is performed on the data obtained by removing the first error processing bit from the processed data, and error processing decoding is performed on the descrambled data. 5. The memory monitoring circuit according to claim 1, wherein the scrambler is a scrambler that scrambles data after being reset by a signal obtained by differentiating a parallel clock indicating a word of data. A memory monitoring circuit characterized by being a descrambler that descrambles data after being reset by a signal obtained by differentiating a parallel clock indicating a word of data.