JP2009284024A - Frame transmission apparatus, and frame transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily detect errors caused in the course of transmission of received frames. <P>SOLUTION: As for dummy data inserted by a dummy data insertion section, the dummy data monitoring section sequentially processes through a scrambling section and a parity generating section, and stores the data in a memory. The stored dummy data is sequentially processed through a series of processing steps through a parity monitoring section and a descrambling section. The dummy data monitoring section compares the dummy data output from the descrambling section with dummy data previously stored in a dummy data storing section, thereby determining whether an error is generated in the series of processing steps. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a frame transmission apparatus and a frame transmission method.

  Conventionally, there is a frame transmission apparatus that transmits a packet frame (see, for example, Patent Document 1).

  Hereinafter, a packet frame transmission process by a conventional frame transmission apparatus will be briefly described with reference to FIG.

  As illustrated in FIG. 6, the frame transmission device 200 is connected via a network so as to be communicable with the upstream device 100 and the downstream device 300 having the same configuration.

  When the frame monitoring unit 201 detects the input of the received frame transmitted from the upstream device 100, the frame monitoring unit 201 generates a timing signal for informing the processing timing of the received frame, and outputs the timing signal to the subsequent processing function unit.

  Next, the FCS monitoring unit 202 checks the received frame using FCS (Frame Check Sequence) data for error detection added to the received frame, and then deletes the FCS data from the received frame to obtain a header. Output to the terminal unit 203.

  The header termination unit 203 outputs a header in the received frame in which an address, a tag, a length, and the like are stored, to the header control unit 204, and cuts out user data in the received frame and outputs the user data to the scramble unit 205.

  The scramble unit 205 scrambles the user data and outputs it to the parity generation unit 206, and the parity generation unit 206 adds the parity to the scrambled user data and outputs it to the memory 207.

  The memory 207 writes the data received from the parity generation unit 206 under the control of the header control unit 204 described later, reads the data, and outputs the data to the parity monitoring unit 208 described later.

  The header control unit 204 manages the address of data stored in the memory 207 and causes the memory 207 to output the stored data to the parity monitoring unit 208. In addition, the header control unit 204 rewrites the header received from the header termination unit 203 and outputs it to the header insertion unit 210.

  The parity monitoring unit 208 performs a parity check on the data received from the memory 207 and outputs the data to the descrambling unit 209. The descrambling unit 209 performs descrambling processing on the data received from the parity monitoring unit 208 and performs header processing. Output to the insertion unit 210.

  The header insertion unit 210 adds the header received from the header control unit 204 to the data received from the descrambling unit 209 and outputs the data to the FCS calculation unit 211.

  The FCS calculation unit 211 performs FCS calculation, adds FCS data to the data received from the header insertion unit 210, and transmits the data to the subsequent apparatus 300 via the network.

JP 2006-197045 A

  However, the conventional frame transmission process described above has a problem in that errors that occur during the transmission process of the received frame may not be detected.

  That is, in the conventional processing, when user data is written in the memory 207, if the parity added to the user data causes a 2-bit error, it is detected even if an error has occurred in the user data. There was a problem that it was not possible.

  Further, there is a problem in that an error in user data generated due to a malfunction of the scramble unit 205 cannot be detected in the same manner.

  It is possible to write and process data in the memory 207 with the FCS for error detection added, but there is a problem that the memory scale must be increased because the data to be written increases.

  Accordingly, the present invention has been made to solve the above-described problems of the prior art, and a frame transmission apparatus and a frame transmission method capable of easily detecting an error that has occurred in the process of transmission processing of a received frame. The purpose is to provide.

  In order to solve the above-described problems and achieve the object, the disclosed apparatus scrambles user data cut out from a received frame, reads data in which parity is added to the scrambled data from a memory, and performs a parity check And a dummy data insertion unit that inserts dummy data at a timing when a received frame that is intermittently input is not detected in a series of processing steps for descrambling the data after parity check, and the dummy data insertion unit An error determination unit that determines whether an error has occurred in the processing process based on the dummy data that has been descrambled by the dummy data inserted in the processing process.

  In addition, the disclosed method scrambles user data cut out from a received frame, reads data in which parity is added to the scrambled data from the memory, performs parity check, and descrambles the data after parity check In a series of processing steps to be processed, dummy data insertion step in which dummy data is inserted at a timing in which a received frame that is intermittently input is not detected, and dummy data inserted in the processing step by the dummy data insertion step are And an error determination step of determining whether an error has occurred in the process based on the dummy data that has been descrambled.

  According to the disclosed apparatus and the disclosed method, it is possible to easily detect an error that has occurred in the process of transmission processing of a received frame.

  Hereinafter, an embodiment of a frame transmission apparatus and a frame transmission method will be described in detail with reference to the accompanying drawings.

[Outline of Frame Transmission Device (Example 1)]
FIG. 1 is a diagram for explaining the outline of the frame transmission apparatus according to the first embodiment.

  As shown in the figure, the frame transmission apparatus according to the first embodiment includes a dummy data insertion unit, a scramble unit, a parity generation unit, a memory, a parity monitoring unit, a descrambling unit, and a dummy data holding unit. And a dummy data monitoring unit.

  Then, the frame transmission apparatus according to the first embodiment processes the user data extracted from the intermittently input received frame in the order of the scramble unit and the parity generation unit described above, stores them in the memory, and then reads from the memory. The outline is to transmit the received frame while performing the process of maintaining the integrity of the received frame by processing the output data in a series of processing steps in order of the parity monitoring unit and the descrambling unit.

  While having the outline as described above, the dummy data insertion unit performs the same dummy data as the dummy data held in advance by the dummy data holding unit at a timing between detection of intermittently received frames. Output to the scramble unit.

  The scramble unit performs scramble processing on the dummy data received from the dummy data insertion unit and outputs the scramble process to the parity generation unit. The parity generation unit adds the parity to the data received from the scramble unit and outputs the data to the memory.

  The parity monitoring unit performs a parity check on the data read from the memory and outputs the data to the descrambling unit. The descrambling unit outputs dummy data obtained by descrambling the data received from the parity monitoring unit to the dummy data monitoring unit.

  The dummy data monitoring unit compares the dummy data received from the descrambling unit with the dummy data held in advance by the dummy data holding unit to determine whether an error has occurred in the above-described series of processing steps. Determine.

  Specifically, the dummy data monitoring unit compares the dummy data received from the descrambling unit with the dummy data held in advance by the dummy data holding unit. It is determined that it has occurred.

  When the dummy data monitoring unit determines that an error has occurred, the frame transmission apparatus according to the first embodiment notifies the management apparatus of an alert that an error has occurred.

  For this reason, the frame transmission apparatus according to the first embodiment can easily detect an error that has occurred in the process of receiving frame transmission processing.

[Configuration of Frame Transmission Device (Example 1)]
FIG. 2 is a diagram illustrating the configuration of the frame transmission apparatus according to the first embodiment.

  As illustrated in FIG. 2, the frame transmission device 400 according to the first embodiment is connected to the upstream device 100 and the downstream device 300 having the same configuration via the network 1 in a communicable state, and the upstream device 100. These are connected in a communicable state with a management apparatus 500 that manages the subsequent apparatus 300 and the frame transmission apparatus 400.

  As shown in FIG. 2, the frame transmission apparatus 400 includes a frame monitoring unit 401, an FCS (Frame Check Sequence) monitoring unit 402, a header termination unit 403, a header control unit 404, a scramble unit 405, a parity Generation unit 406, memory 407, parity monitoring unit 408, descrambling unit 409, header insertion unit 410, FCS calculation unit 411, dummy data insertion unit 412, dummy data holding unit 413, dummy data monitoring Unit 414 and an alert notification unit 415.

  The frame monitoring unit 401 is a processing unit that detects an input of a received frame transmitted from the preceding apparatus 100. When detecting an input of a received frame transmitted from the preceding apparatus 100, the frame monitoring unit 401 notifies the processing timing of the received frame. A timing signal is generated and output to the subsequent processing function units (FCS monitoring unit 402, header termination unit 403, and header control unit 404).

  In addition, when the frame monitoring unit 401 detects a gap in which a reception frame that is intermittently input is not detected, the frame monitoring unit 401 generates a timing signal (for example, “a”) indicating a timing in which the reception frame is not detected. To the header control unit 404.

  The FCS monitoring unit 402 is a processing unit that checks a received frame using FCS (Frame Check Sequence) data for error detection added to the received frame. After checking the received frame, the received frame FCS data is deleted from the header and output to the header termination unit 403.

  The header termination unit 403 is a processing unit that processes the data received from the FCS monitoring unit 402. The header termination unit 403 outputs a header in a received frame in which an address, a tag, a length, and the like are stored to the header control unit 404, and receives the received frame. The user data is cut out and output to the scramble unit 405.

  The scramble unit 405 is a processing unit that scrambles user data received from the header termination unit 403.

  Specifically, the scramble unit 405 performs scramble processing on user data received from the header termination unit 403 or dummy data received from a dummy data insertion unit 412 described later, and outputs the result to the parity generation unit 406.

  The scramble process is an encoding process for eliminating the influence of noise generated by simultaneous switching on user data, and all the data widths to be stored in the memory are simultaneously changed to “1” or “0”. However, through the scramble process, data can be distributed (or averaged) to a mixture of “1” and “0”, and simultaneous switching can be reduced.

  The parity generation unit 406 is a processing unit that adds parity to data received from the scramble unit 405 or dummy data, and outputs the data or dummy data to which the parity is added to the memory 407.

  The header control unit 404 has a memory control function for managing the address of data stored in the memory 407 and controlling writing to the memory 407 and reading from the memory 407, and the header received from the header termination unit 403. Is a processing unit for rewriting.

  Specifically, the header control unit 404 notifies the write address to the memory 407, stores the data output from the parity generation unit 406, notifies the read address to the memory 407, and sets the read data to the parity. The monitoring unit 408 outputs the data.

  In addition, the header control unit 404 rewrites the header received from the header termination unit 403 with the address of the subsequent apparatus 300 and outputs it to the header insertion unit 410.

  Furthermore, when the header control unit 404 receives a timing signal (for example, “a”) indicating the interval between the frames in which the received frame that is intermittently input is not detected from the frame monitoring unit 401, the header control unit 404 detects the interval in which the received frame is not detected. Is calculated.

  The header control unit 404 performs the above-described series of processing steps (a series of processing steps in which data is processed in the order of the scramble unit 405, the parity generation unit 406, the memory 407, the parity monitoring unit 408, and the descrambling unit 409). When the interval between the dummy data insertion times is detected, a dummy data insertion request (for example, “b”) is output to the dummy data insertion unit 412.

  Along with the output of the dummy data insertion request, the header control unit 404 notifies the memory 407 of the write address of the dummy data output from the parity generation unit 406 to the memory 407 by the memory control function described above, and causes the dummy data to be written. At the same time, the memory 407 is notified of the read address of the dummy data so that the dummy data is read and also output to the parity monitoring unit 408.

  When notifying the memory 407 of the dummy data read address, the header control unit 404 outputs a dummy data read notification signal (eg, “c”) to the dummy data monitoring unit 414.

  Under the control of the header control unit 404 described above, the memory 407 writes the data received from the parity generation unit 406 or dummy data, reads the written data or dummy data, and outputs it to the parity monitoring unit 408. .

  The parity monitoring unit 408 is a processing unit that performs a parity check of data received from the memory 407 or dummy data, performs a parity check of the data received from the memory 407 or dummy data, and outputs the data to the descrambling unit 409.

  The descrambling unit 409 is a processing unit that performs descrambling processing on the data received from the parity monitoring unit 408 or dummy data, and performs descrambling processing on the data received from the parity monitoring unit 408 to be described later. To the dummy data monitoring unit 414.

  The descrambling process is a process of decoding the scrambled data into the original data.

  The header insertion unit 410 adds the header received from the header control unit 404 to the data received from the dummy data monitoring unit 414 described later, and outputs the data to the FCS calculation unit 411.

  The FCS calculation unit 411 performs FCS calculation, adds FCS data to the data received from the header insertion unit 410, and transmits the data to the subsequent apparatus 300 via the network 1.

  The dummy data insertion unit 412 performs the above-described series of processing steps (the scramble unit 405, the parity generation unit 406, the memory 407, the parity monitoring unit 408, and the descrambling unit at a timing between detection of intermittently received frames. The processing unit inserts dummy data into a series of processing steps in which data is processed in the order of 409.

  Specifically, when the dummy data insertion unit 412 receives a dummy data insertion request from the header control unit 404, the dummy data insertion unit 412 inserts into the scramble unit 405 the same dummy data as the dummy data held in the dummy data holding unit 413 described later. To do.

  The dummy data holding unit 413 is a holding unit that holds the same dummy data as the dummy data inserted by the dummy data insertion unit 412.

  The dummy data monitoring unit 414 compares the dummy data output from the descrambling unit 409 through the above-described series of processing steps with the dummy data held in advance by the dummy data holding unit 413, so that It is a determination unit that determines whether or not an error has occurred in the series of processing steps.

  Specifically, when the dummy data monitoring unit 414 receives a dummy data read notification signal (for example, “c”) from the header control unit 404, the dummy data monitoring unit 414 sets the data received from the descrambling unit 409 as dummy data. As a result of comparing and comparing the dummy data with the dummy data held in advance by the dummy data holding unit 413, if the dummy data does not match, it is determined that an error has occurred.

  If the dummy data monitoring unit 414 determines that an error has occurred in the series of processing steps described above, the dummy data monitoring unit 414 outputs an alert notification instruction to the management device 500 to the alert notification unit 415 described later.

  If the dummy data monitoring unit 414 has not received a dummy data read notification signal (for example, “c”) from the header control unit 404, the dummy data monitoring unit 414 directly inputs the data received from the descrambling unit 409 to the header insertion unit 410. Output.

  The alert notification unit 415 is a processing unit that notifies the management device 500 of a warning. When an alert notification instruction is received from the dummy data monitoring unit 414, an alert indicating that an error has occurred via the network 1 To the management apparatus 500.

  The functions such as the frame monitoring unit 401, the header control unit 404, the dummy data insertion unit 412, the dummy data holding unit 413, and the dummy data monitoring unit 414 described above are functioning as an ASIC (Application Specific Integrated Circuit) in the frame transmission apparatus. And FPGA (Field Programmable Gate Array).

[Processing of frame transmission apparatus (first embodiment)]
FIG. 3 is a diagram illustrating the flow of processing by the frame transmission apparatus according to the first embodiment.

  As illustrated in FIG. 3, when the frame monitoring unit 401 detects a gap where an intermittently received reception frame is not detected (Yes in step S <b> 301), the frame monitoring unit 401 generates a timing signal indicating the timing of a gap where the reception frame is not detected. Generate and output to the header control unit 404 (step S302).

  When the header control unit 404 receives from the frame monitoring unit 401 a timing signal indicating the timing of a gap in which an intermittently received reception frame is not detected, the header control unit 404 can calculate the interval in which no reception frame is detected and insert dummy data When the time between the gaps is detected, a dummy data insertion request is output to the dummy data insertion unit 412 (step S303).

  When the dummy data insertion unit 412 receives the dummy data insertion request from the header control unit 404, the dummy data insertion unit 412 inserts the same dummy data as the dummy data held in the dummy data holding unit 413, which will be described later, into the scramble unit 405 (step S304). .

  The scramble unit 405 scrambles the dummy data received from the dummy data insertion unit 412 (step S305).

  After the scramble processing, the parity generation unit 406 adds parity to the dummy data output from the scramble unit 405 and outputs the dummy data to the memory 407. The memory 407 generates a parity under the control of the header control unit 404. The dummy data received from the unit 406 is written (step S306).

  Subsequently, under the control of the header control unit 404, the memory 407 reads dummy data and outputs it to the parity monitoring unit 408. The parity monitoring unit 408 performs a parity check of the dummy data received from the memory 407 (step S307).

  The descrambling unit 409 performs descrambling processing on the dummy data output from the parity monitoring unit 408 after the parity check (step S308).

  The dummy data monitoring unit 414 determines whether or not the dummy data output from the descrambling unit 409 matches the dummy data held in advance by the dummy data holding unit 413 (step S309).

  As a result of the determination, if the dummy data output from the descrambling unit 409 and the dummy data held in advance by the dummy data holding unit 413 do not match (No in step S309), the dummy data monitoring unit 414 Then, it is determined that an error has occurred in a series of processing steps, and an alert notification instruction for the management apparatus 500 is output to the alert notification unit 415 (step S310).

  On the other hand, when the dummy data output from the descrambling unit 409 matches the dummy data held in advance by the dummy data holding unit 413 (Yes in step S309), the dummy data monitoring unit 414 performs a series of operations. It is determined that an error has not occurred in the process of (1), and the insertion of the next dummy data is awaited.

[Effects of Example 1]
As described above, according to the first embodiment, it is possible to easily detect an error that has occurred in the process of transmission processing of a received frame.

  In addition, since it is not necessary to write and process data in the memory with the FCS for error detection added, it is necessary to increase the memory scale in order to easily detect an error that has occurred during the transmission processing of the received frame. There is no effect.

  In the first embodiment, the dummy data monitoring unit 414 matches the dummy data output from the descrambling unit 409 via a series of processing steps with the dummy data held in advance by the dummy data holding unit 413. A case has been described in which it is determined whether or not an error has occurred in a series of processing steps.

  However, as described in the first embodiment, the present invention is not limited to determining whether an error has occurred. The configuration and processing of the frame transmission apparatus according to the second embodiment will be described in order below.

[Configuration of Frame Transmission Device (Example 2)]
FIG. 4 is a block diagram illustrating the configuration of the frame transmission apparatus according to the second embodiment. The configuration of the frame transmission apparatus 400 according to the second embodiment is different from the frame transmission apparatus according to the first embodiment in the points described below.

  That is, the frame transmission apparatus 400 according to the second embodiment includes an expected value holding unit 416 instead of the dummy data holding unit 413.

  The expected value holding unit 416 previously holds, as an expected value, the same value as the calculated value obtained by the CRC (Cyclic Redundancy Check) calculation of the dummy data inserted in the above-described series of processing steps by the dummy data inserting unit 412. To do.

  Then, the dummy data monitoring unit 414 performs CRC calculation on the dummy data output from the descrambling unit 409 through the above-described series of processing steps, and the calculation value obtained as the calculation result and the expected value holding unit 416 in advance. By comparing the stored expected value, it is determined whether or not an error has occurred in the series of processing steps described above.

  Specifically, when the dummy data monitoring unit 414 receives a dummy data read notification signal (for example, “c”) from the header control unit 404, the dummy data monitoring unit 414 performs CRC calculation on the data received from the descrambling unit 409. .

  Then, the dummy data monitoring unit 414 compares the calculated value obtained as the CRC calculation result with the expected value held in advance by the expected value holding unit 416, and if the calculated value does not match the expected value, It is determined that an error has occurred.

[Processing of frame transmission apparatus (second embodiment)]
FIG. 5 is a diagram illustrating the flow of processing by the frame transmission apparatus according to the second embodiment. The processing flow of the frame transmission apparatus 400 according to the second embodiment is different from the processing flow of the frame transmission apparatus according to the first embodiment in the points described below.

  That is, as shown in FIG. 5, the dummy data monitoring unit 414 performs CRC calculation on the data received from the descrambling unit 409, and the calculated value obtained as a CRC calculation result and the expected value holding unit 416 are held in advance. It is determined whether or not the expected value matches (step S509).

  As a result of the determination, when the calculated value obtained as the CRC calculation result does not match the expected value held in advance by the expected value holding unit 416 (No in step S509), the dummy data monitoring unit 414 performs a series of operations. In step S510, it is determined that an error has occurred in the processing step, and an alert notification instruction to the management apparatus 500 is output to the alert notification unit 415 (step S510).

[Effects of Example 2]
As described above, according to the second embodiment, the dummy data holding unit 413 does not hold the dummy data in advance, but the expected value holding unit 416 holds the calculated value obtained by performing the CRC calculation on the dummy data as the expected value. The load for holding data can be reduced compared to holding dummy data itself.

  In the first and second embodiments described above, during the normal frame transmission processing in the frame transmission device 400, an error that occurs in a series of processing steps is aimed at the timing of a gap in which a received frame is not detected. The case of detection was explained.

  However, the disclosed frame transmission apparatus is not limited to this. For example, when checking whether an error occurs in a series of processing steps by inserting dummy data at a stage before product shipment. Can be applied similarly.

  The frame transmission apparatus 400 of the present disclosure may be implemented in various different forms other than the above-described embodiments. Accordingly, other embodiments will be described below.

(1) Device Configuration, etc. Each component of the frame transmission device 400 shown in FIGS. 2 and 4 is functionally conceptual and does not necessarily need to be physically configured as illustrated. That is, the specific form of distribution / integration of the frame transmission apparatus 400 is not limited to the illustrated one.

  For example, the dummy data holding unit 413 and the dummy data monitoring unit 414 shown in FIG. 2 are integrated, and the dummy data monitoring unit 414 and the expected value holding unit 416 shown in FIG. It can be configured to be functionally or physically distributed / integrated in arbitrary units according to various loads or usage conditions.

  Furthermore, each processing function (for example, refer to FIG. 3 and FIG. 5) performed in the frame transmission apparatus 400 is realized by a CPU and a program that is analyzed and executed by the CPU. Alternatively, it can be realized as hardware by wired logic.

(2) Frame Transmission Method The following frame transmission method is realized by the frame transmission device 400 described in the above embodiment.

  That is, a series of processes that scramble user data cut out from a received frame, read data with parity added to the scrambled data from the memory, perform parity check, and descramble the data after parity check In the process, a dummy data insertion step (see, for example, step S304 in FIG. 3) in which dummy data is inserted at intervals between which no intermittently received reception frame is detected, and the dummy data insertion step makes a series of processing steps. An error determination step for determining whether or not an error has occurred in a series of processes based on the dummy data in which the inserted dummy data has been descrambled (see, for example, step S309 in FIG. 3). Including frame transmission method That.

  Regarding the embodiment including the above-described examples, the following additional notes are further disclosed.

(Supplementary note 1) A series of scramble processing on user data cut out from a received frame, reading data in which parity is added to the scrambled data from the memory, performing a parity check, and descrambling the data after the parity check A dummy data insertion unit that inserts dummy data at a timing in which a received frame that is intermittently input is not detected in the processing process;
An error determination unit that determines whether an error has occurred in the process based on the dummy data that has been descrambled by the dummy data inserted in the process by the dummy data insertion unit;
A frame transmission apparatus comprising:

(Additional remark 2) It further has the dummy data holding part which hold | maintains previously the same dummy data as the dummy data inserted in the said process by the said dummy data insertion part,
The error determination unit determines whether an error has occurred in the processing process based on a comparison result of comparing the dummy data that has been descrambled with the dummy data held in the dummy data holding unit. The frame transmission apparatus as set forth in appendix 1, wherein the frame transmission apparatus determines whether or not.

(Additional remark 3) It further has the calculation value holding part which hold | maintains beforehand the calculation value by which the dummy data inserted in the said process by the said dummy data insertion part was CRC calculation processed,
The error determination unit performs a process based on a comparison result obtained by comparing a calculation value obtained by performing CRC calculation processing on the descrambled dummy data and a calculation value held in the calculation value holding unit. The frame transmission apparatus according to appendix 1, wherein it is determined whether or not an error has occurred.

(Supplementary Note 4) When the error determination unit determines that an error has occurred in the processing process, the error determination unit further includes a warning notification unit that notifies the management apparatus that manages the frame transmission apparatus of a warning. The frame transmission apparatus according to appendix 1, wherein

(Supplementary note 5) A series of scramble processing on user data cut out from a received frame, reading data in which parity is added to the scrambled data from the memory, performing a parity check, and descrambling the data after the parity check A dummy data insertion step for inserting dummy data at a timing in which a received frame that is intermittently input is not detected in the process of
An error determination step for determining whether an error has occurred in the process based on the dummy data in which the dummy data inserted in the process in the dummy data insertion step has been descrambled; and
A frame transmission method comprising:

(Supplementary Note 6) In the error determination step, the dummy data that has been subjected to the descrambling process is compared with the dummy data that is stored in advance and that is the same dummy data that is inserted in the process in the dummy data insertion step. 6. The frame transmission method according to appendix 5, wherein it is determined whether an error has occurred in the process based on a comparison result.

(Additional remark 7) The calculation value holding step which hold | maintains beforehand the calculation value by which the dummy data inserted in the said process in the said dummy data insertion step carried out CRC calculation processing is further included,
In the error determination step, a calculation value obtained by performing CRC calculation processing on the dummy data that has been subjected to the descrambling processing and a dummy data inserted in the processing process by the dummy data insertion step that is stored in advance are subjected to CRC calculation processing. 6. The frame transmission method according to appendix 5, wherein whether or not an error has occurred in the processing process is determined based on a comparison result obtained by comparing the calculated value.

(Supplementary Note 8) When it is determined by the error determination step that an error has occurred in the processing process, the error determination step further includes a warning notification step of notifying the management apparatus that manages the frame transmission apparatus. The frame transmission method according to appendix 5, which is characterized by the above.

1 is a diagram for explaining an overview of a frame transmission apparatus according to Embodiment 1. FIG. 1 is a diagram illustrating a configuration of a frame transmission apparatus according to Embodiment 1. FIG. FIG. 6 is a diagram illustrating a process flow of the frame transmission apparatus according to the first embodiment. FIG. 6 is a diagram illustrating a configuration of a frame transmission apparatus according to a second embodiment. FIG. 10 is a diagram illustrating a processing flow of the frame transmission apparatus according to the second embodiment. It is a figure which shows the conventional structure of a frame transmission apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Network 100 Pre-stage apparatus 300 Post-stage apparatus 400 Frame transmission apparatus 401 Frame monitoring part 402 FCS (Frame Check Sequence) monitoring part 403 Header termination part 404 Header control part 405 Scramble part 406 Parity generation part 407 Memory 408 Parity monitoring part 409 Descramble part 410 Header Insertion Unit 411 FCS Operation Unit 412 Dummy Data Insertion Unit 413 Dummy Data Holding Unit 414 Dummy Data Monitoring Unit 415 Alert Notification Unit 416 Expected Value Holding Unit 500 Management Device

Claims (5)

The user data cut out from the received frame is scrambled, the data with parity added to the scrambled data is read from the memory, the parity check is performed, and the data after the parity check is descrambled. A dummy data insertion unit that inserts dummy data at a timing in which a received frame that is intermittently input is not detected;
An error determination unit that determines whether an error has occurred in the process based on the dummy data that has been descrambled by the dummy data inserted in the process by the dummy data insertion unit;
A frame transmission apparatus comprising: A dummy data holding unit that holds in advance dummy data that is the same as the dummy data inserted in the process by the dummy data insertion unit;
The error determination unit determines whether an error has occurred in the processing process based on a comparison result of comparing the dummy data that has been descrambled with the dummy data held in the dummy data holding unit. The frame transmission device according to claim 1, wherein the frame transmission device determines whether or not. The dummy data insertion unit further includes a calculation value holding unit that holds in advance a calculation value obtained by performing CRC calculation processing on the dummy data inserted in the processing step,
The error determination unit performs a process based on a comparison result obtained by comparing a calculation value obtained by performing CRC calculation processing on the descrambled dummy data and a calculation value held in the calculation value holding unit. The frame transmission apparatus according to claim 1, wherein it is determined whether an error has occurred.   When the error determination unit determines that an error has occurred in the processing process, the error determination unit further includes a warning notification unit that notifies the management device that manages the frame transmission device of a warning. The frame transmission apparatus according to claim 1. The user data cut out from the received frame is scrambled, the data with parity added to the scrambled data is read from the memory, the parity check is performed, and the data after the parity check is descrambled. , A dummy data insertion step for inserting dummy data at a timing between detection of intermittently received reception frames;
An error determination step for determining whether an error has occurred in the process based on the dummy data in which the dummy data inserted in the process in the dummy data insertion step has been descrambled; and
A frame transmission method comprising:

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