KR970049426A - Data transformation method - Google Patents
Data transformation method Download PDFInfo
- Publication number
- KR970049426A KR970049426A KR1019950062146A KR19950062146A KR970049426A KR 970049426 A KR970049426 A KR 970049426A KR 1019950062146 A KR1019950062146 A KR 1019950062146A KR 19950062146 A KR19950062146 A KR 19950062146A KR 970049426 A KR970049426 A KR 970049426A
- Authority
- KR
- South Korea
- Prior art keywords
- data
- byte unit
- clock signal
- transformation method
- data transformation
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Image Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
본 발명은 데이터 변환 방법에 관해 게시한다. 종래에는 비트 단위의 데이터를 바이트 단위의 데어터로 변환시 직렬적인 방법을 사용함으로 인해 변환 시간이 늦었으나, 본 발명에 따르면 병렬적인 방법을 사용하고 또 상태 바이트를 이용하여 데이터의 동기상태를 탐색함으로써 데이터 변환 시간을 2배 내지 3배 빠르게 할 수 있다.The present invention discloses a data conversion method. Conventionally, the conversion time is slow because a serial method is used to convert data in bits to data in bytes. However, according to the present invention, data is obtained by using a parallel method and searching for a synchronous state of data using status bytes. The conversion time can be 2 to 3 times faster.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명에 의하여 직렬 데이터를 병렬 데이터로 변환하는 방법을 설명하기 위한 클럭신호들의 타이밍도,1 is a timing diagram of clock signals for explaining a method of converting serial data into parallel data according to the present invention;
제3도는 상기 제1도의 병렬 데이터의 동기방법을 설명하기 위하여 도시한 도면.3 is a diagram for explaining a method of synchronizing parallel data of FIG.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950062146A KR100411231B1 (en) | 1995-12-28 | 1995-12-28 | Method for converting data |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950062146A KR100411231B1 (en) | 1995-12-28 | 1995-12-28 | Method for converting data |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970049426A true KR970049426A (en) | 1997-07-29 |
KR100411231B1 KR100411231B1 (en) | 2004-03-18 |
Family
ID=37422894
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950062146A KR100411231B1 (en) | 1995-12-28 | 1995-12-28 | Method for converting data |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100411231B1 (en) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5673952A (en) * | 1979-11-22 | 1981-06-19 | Toshiba Corp | Serial-parallel conversion system |
KR880003598Y1 (en) * | 1985-08-24 | 1988-10-12 | 삼성전자 주식회사 | Pararell modulating circuit of a direct data |
JPH04267430A (en) * | 1991-02-22 | 1992-09-24 | Seiko Epson Corp | Serial/parallel converter |
KR950009772Y1 (en) * | 1991-08-29 | 1995-11-22 | Lg정보통신 주식회사 | Data convert circuit |
KR950013806B1 (en) * | 1993-03-05 | 1995-11-16 | 삼성전자주식회사 | Serial/parallel conversion method and device of data |
JP3095590B2 (en) * | 1993-09-24 | 2000-10-03 | 株式会社東芝 | Circuit breaker |
-
1995
- 1995-12-28 KR KR1019950062146A patent/KR100411231B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100411231B1 (en) | 2004-03-18 |
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