KR970029054A

KR970029054A - Input / output connection device for digital signal processing for FPLA verification

Info

Publication number: KR970029054A
Application number: KR1019950043450A
Authority: KR
Inventors: 고성규
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1995-11-24
Filing date: 1995-11-24
Publication date: 1997-06-26

Abstract

본 발명은 FPLA검증을 위한 검증신호처리수단과 FPLA보드와의 연결이 자유롭게 이루어질 수 있도록 하는 FPLA검증용 디지털신호처리를 위한 입/출력연결장치를 제공한다.The present invention provides an input / output connection device for digital signal processing for FPLA verification that allows the connection between the verification signal processing means for FPLA verification and the FPLA board can be freely made.

그에 따라 본 발명은 FPGA보드(32)의 검증을 위한 검증신호처리수단(30)에 있어서; 상기 검증신호처리수단(30)으로부터의 32비트의 출력데이터를 각각 입력하여 상기 FPGA보드(34)에 출력함과 더블어, 그 FPGA보드(32)로부터의 32비트의 결과데이터를 각각 입력받아 상기 검증신호처리수단(30)에 출력하는 입/출력셀(a0~h3)과, 상기 입/출력셀(a0~h3)의 입력 또는 출력상태의 지정이 변경가능하도록 형성된 출력경로풀(36A~36H; ORP), 상기 출력경로풀(36A~36H)를 통해 상기 입/출력셀(a0~h3)의 16개마다 각각 연결되어 논리기능을 수행하는 1쌍의 포괄논리블럭(A0~H3; Twin GLB) 및, 상기 1쌍의 포괄논리블럭(A0~H3)을 통한 디지털데이터를 입력받아 딜레이시켜 출력하는 전역경로풀(44;GRP)을 갖춘 입/출력연결수단(34)을 구비하여 구성된 것을 특징으로 한다.Accordingly, the present invention provides a verification signal processing means for verifying the FPGA board 32; 32-bit output data from the verification signal processing means 30 are respectively inputted and output to the FPGA board 34, and the 32-bit result data from the FPGA board 32 is input to the verification. Input / output cells a0 to h3 output to the signal processing means 30, and output path pools 36A to 36H formed to be able to change an input or output state of the input / output cells a0 to h3; ORP) and a pair of comprehensive logic blocks (A0 to H3; Twin GLB), each of which is connected to each of the input / output cells a0 to h3 through the output path pools 36A to 36H to perform logic functions. And an input / output connection unit 34 having a global path pool 44 (GRP) for receiving and delaying digital data through the pair of comprehensive logic blocks A0 to H3. do.

Description

Input / output connection device for digital signal processing for FPLA verification

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 적용되는 FPLA검증용 디지털신호처리장치를 나타낸 블럭구성도,1 is a block diagram showing a digital signal processing apparatus for verifying FPLA applied to the present invention;

제2도는 본 발명에 따른 FPLA검증용 디지털신호처리를 위한 입/출력연결장치를 나타낸 블럭구성도이다.2 is a block diagram showing an input / output connection device for digital signal processing for FPLA verification according to the present invention.

Claims

Verification signal processing means (30) for verifying the FPGA board (32); 32-bit output data from the verification signal processing means 30 is input to the FPLA board 34, and 32-bit result data from the FPGA board 32 is input to the verification. Input / output cells a0 to h3 output to the signal processing means 30, and output path pools 36A to 36H formed to be able to change an input or output state of the input / output cells a0 to h3; ORP) and a pair of comprehensive logic blocks (A0 to H3; Twin GLB), each of which is connected to each of the input / output cells a0 to h3 through the output path pools 36A to 36H to perform logic functions. And an input / output connection unit 34 having a global path pool 44 (GRP) for receiving and delaying digital data through the pair of comprehensive logic blocks A0 to H3. Input / output connection device for digital signal processing for FPLA verification.

※ Note: The disclosure is based on the initial application.