KR970002613A - Zero bit string detection circuit - Google Patents
Zero bit string detection circuit Download PDFInfo
- Publication number
- KR970002613A KR970002613A KR1019950019163A KR19950019163A KR970002613A KR 970002613 A KR970002613 A KR 970002613A KR 1019950019163 A KR1019950019163 A KR 1019950019163A KR 19950019163 A KR19950019163 A KR 19950019163A KR 970002613 A KR970002613 A KR 970002613A
- Authority
- KR
- South Korea
- Prior art keywords
- bit string
- zero bit
- input
- signal
- zero
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/06—Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
본 발명은 제로 비트 스트링 검출 회로에 관한 것으로, 비트 입력을 입력으로 하는 다수의 비트 입력수단; 상기 다수의비트 입력 수단의 각 드레인 및 소오스에 각각 연결되어 제로 비트 스트링 검출 조절 신호를 출력하는 제로 비트 스트링검출 조절수단; 및 상기 다수의 비트 입력 수단의 각 드레인 및 소오스에 각각 연결되어 제로 비트 스트링 입력 검출 신호를 출력하는 제로 비트 스트링 입력 검출수단을 구비하며, 제로 비트 스트링 검출에 소요되는 시간과 에리어를 감소시킬 수 있는 효과가 있다.The present invention relates to a zero bit string detection circuit, comprising: a plurality of bit input means for inputting a bit input; Zero bit string detection adjusting means connected to each drain and source of the plurality of bit input means, respectively, and outputting a zero bit string detection adjusting signal; And zero bit string input detection means connected to respective drains and sources of the plurality of bit input means, respectively, and outputting a zero bit string input detection signal, the time and area required for zero bit string detection being reduced. It works.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 제로 비트 스트링 검출회로도, 제5도는 일반적인 오퍼랜드 수치 연산 수행 흐름도.2 is a zero bit string detection circuit diagram according to the present invention, and FIG. 5 is a flowchart of performing a general operand numerical operation.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019163A KR0147707B1 (en) | 1995-06-30 | 1995-06-30 | Zero bit string detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019163A KR0147707B1 (en) | 1995-06-30 | 1995-06-30 | Zero bit string detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970002613A true KR970002613A (en) | 1997-01-28 |
| KR0147707B1 KR0147707B1 (en) | 1998-09-15 |
Family
ID=19419511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950019163A KR0147707B1 (en) | 1995-06-30 | 1995-06-30 | Zero bit string detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0147707B1 (en) |
-
1995
- 1995-06-30 KR KR1019950019163A patent/KR0147707B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR0147707B1 (en) | 1998-09-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050422 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |