KR960020512A - Line length decoder - Google Patents

Line length decoder Download PDF

Info

Publication number
KR960020512A
KR960020512A KR1019940032344A KR19940032344A KR960020512A KR 960020512 A KR960020512 A KR 960020512A KR 1019940032344 A KR1019940032344 A KR 1019940032344A KR 19940032344 A KR19940032344 A KR 19940032344A KR 960020512 A KR960020512 A KR 960020512A
Authority
KR
South Korea
Prior art keywords
zero
signal
detection signal
level
processing means
Prior art date
Application number
KR1019940032344A
Other languages
Korean (ko)
Other versions
KR100275268B1 (en
Inventor
손영석
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019940032344A priority Critical patent/KR100275268B1/en
Publication of KR960020512A publication Critical patent/KR960020512A/en
Application granted granted Critical
Publication of KR100275268B1 publication Critical patent/KR100275268B1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/93Run-length coding
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

본 발명의 줄길이복호화기(Run Length Decoder : RLD)한 클럭에 2펠씩 처리할 수 있으므로, 후단의 가변질이복호화기(Variable Lenght Decoder :VLD) 처리속도를 향상시킬 수 있는데, 두개의 펠의 런 (run)값을 각각 래치하고, 래치된 런값이 영인지를 각각 판별하여 영이 판별될 경우 각각의 제1영검출신호 및 제2영검출신호를 출력하고, 영이 판별되지 않을 경우 런값에서 2씩 감산하고 감산한 결과가 영인지 일인지를 검출하여 영이 검출될 경우 제3영검출 신호 출력하고, 일이 검출될 경우 일검출신호를 출력하는 런처리수단과, 상기 런처리수단으로부터 제1영검출신호, 제2영검출신호, 제3영검출신호 및 일검출신호에 응답하여 다수의 선택신호를 생성하여 상기 런처리수단 및 레벨처리수단으로 제공하는 제어수단과, 상기 두개의 펠의 레벨에 해당하는 제1레벨신호 및 제2레벨신호를 입력으로 하여 상기 제1레벨신호를 래치한 제3레벨신호 및 영신호를 발생하고 상기 제2레벨신호, 상기 제2레벨신호, 상기 제3레벨신호 및 상기 영신호중 하나를 상기 제어수단의 선택신호에 응답하여 선택하는 상기 레벨처리수단을 포함하는 줄길이복호화기에 의해 달성된다.Since the run length decoder (RLD) of the present invention can process two pels in one clock, it is possible to improve the processing speed of a variable lenght decoder (VLD) in the rear stage. Each run value is latched, and whether the latched run value is zero, respectively, and if zero is determined, each of the first zero detection signal and the second zero detection signal is output. Run processing means for detecting whether the result of subtraction and subtraction is zero or one, and outputting a third zero detection signal when zero is detected, and outputting a one detection signal when one is detected; and a first zero detection signal from the run processing means. And control means for generating a plurality of selection signals in response to the second zero detection signal, the third zero detection signal, and the one detection signal, and providing them to the run processing means and the level processing means. First level signal and A second level signal is input to generate a third level signal and a zero signal latching the first level signal, and one of the second level signal, the second level signal, the third level signal, and the zero signal is generated. By a line length decoder comprising said level processing means for selecting in response to a selection signal of the control means.

Description

줄길이복호화기Line length decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 줄길이복호화기를 도시하는 도면,2 is a diagram showing a string length decoder according to the present invention;

제3도는 줄길이복호화기의 제어부의 동작을 설명하는 도면.3 is a diagram for explaining the operation of the controller of the string length decoder.

Claims (1)

두개의 펠의 런값을 각각 래치하고, 래치된 런값이 영인지를 각각 판별하여 영이 판별될 경우 각각의 제1영검출신호 및 제2영검출신호를 출력하고, 영이 판별되지 않을 경우 런값에서 2씩 감산하고 감산한 결과가 영인지 일인지를 검출하여 영이 검출될 경우 제3영검출신호출력하고, 일이 검출될 경우 일검출신호를 출력하는 런처리수단과; 상기 런처리수단으로 부터 제1영검출신호, 제2영검출신호, 제3영검출신호 및 일검출신호에 응답하여 다수의 선택신호를 생성하여 상기 런처리수단 및 레벨처리 수단으로 제공하는 제어수단과; 상기 두개의 펠의 레벨에 해당하는 제1레벨신호 및 제2레벨신호를 입력으로 하여 상기 제1레벨신호를 래치한 제3레벨신호 및 영신호를 발생하고 상기 제1레벨신호, 상기 제2레벨신호, 상기 제3레벨신호 및 상기 영신호중 하나를 상기 제어수단의 선택신호에 응답하여 선택하는 상기 레벨처리수단을 포함하는 줄길이복호화기.The run values of the two pels are latched, respectively, and each of the latched run values is determined to be zero. If zero is determined, each of the first zero detection signal and the second zero detection signal is output. Run processing means for detecting whether the result of subtraction and subtraction is zero or one, outputting a third zero detection signal if zero is detected, and outputting a one detection signal if one is detected; Control means for generating a plurality of selection signals in response to the first zero detection signal, the second zero detection signal, the third zero detection signal, and the one detection signal from the run processing means and providing them to the run processing means and the level processing means; and; A first level signal and a second level signal corresponding to the two pel levels are input to generate a third level signal and a zero signal latching the first level signal, and the first level signal and the second level. And said level processing means for selecting one of a signal, said third level signal, and said zero signal in response to a selection signal of said control means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940032344A 1994-11-30 1994-11-30 Run length decoder KR100275268B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940032344A KR100275268B1 (en) 1994-11-30 1994-11-30 Run length decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940032344A KR100275268B1 (en) 1994-11-30 1994-11-30 Run length decoder

Publications (2)

Publication Number Publication Date
KR960020512A true KR960020512A (en) 1996-06-17
KR100275268B1 KR100275268B1 (en) 2000-12-15

Family

ID=19399984

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940032344A KR100275268B1 (en) 1994-11-30 1994-11-30 Run length decoder

Country Status (1)

Country Link
KR (1) KR100275268B1 (en)

Also Published As

Publication number Publication date
KR100275268B1 (en) 2000-12-15

Similar Documents

Publication Publication Date Title
KR970705292A (en) A key signal generating device, a picture synthesizing device, a key signal generating method, and a picture synthesizing method (a key signal generating device and a picture producing device)
KR960020510A (en) Line length decoder
KR930014040A (en) Address transition detection circuit
KR960020512A (en) Line length decoder
KR950024433A (en) Data output circuit and semiconductor memory
KR930005366A (en) Device and method for outputting valid data only and memory device
KR930005477A (en) Image processing device
KR950025340A (en) Microwave encoder key input device and interrupt processing method using the device
KR910021030A (en) Skew clamp circuit
KR830009850A (en) Mode discrimination circuit
KR970055227A (en) Voltage sensor
KR960038972A (en) Output circuit of sense amplifier
KR950022543A (en) Dedicated line selection circuit of digital key phone system
KR930008837A (en) Bank signal control circuit
KR970057954A (en) Output device of motion estimator
KR960016525A (en) Motion vector decoder
KR920004853A (en) Automatic inspection circuit and its control method
KR930014071A (en) Interrupt controller
KR970049578A (en) Memory control circuit
KR970002613A (en) Zero bit string detection circuit
KR950020061A (en) User code assignment circuit
KR970003051A (en) Spindle motor control signal generator of optical disk device
KR960019993A (en) Input device of general purpose controller
KR970024574A (en) Phase detection method and circuit
KR960002004A (en) Flexible Address Controller in Extended ROM Area

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110901

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20120903

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee