KR970018051A - Method for forming contact hole in semiconductor device having double insulating film - Google Patents

Method for forming contact hole in semiconductor device having double insulating film Download PDF

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Publication number
KR970018051A
KR970018051A KR1019950031387A KR19950031387A KR970018051A KR 970018051 A KR970018051 A KR 970018051A KR 1019950031387 A KR1019950031387 A KR 1019950031387A KR 19950031387 A KR19950031387 A KR 19950031387A KR 970018051 A KR970018051 A KR 970018051A
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South Korea
Prior art keywords
insulating film
film
forming
hole
layer
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KR1019950031387A
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Korean (ko)
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KR100362472B1 (en
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윤영식
황득진
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 층 상에 형성되며, 고전압에 견딜 수 있도록 충분한 두께의 제1절연막 및 이 위의 제2절연막을 형성하고, 상기 반도체 층과 도전층과의 접촉을 위한 접촉홀을 형성하기 위한 접촉홀 형성하기 위해서, 제2절연막 상에 포토레지스트막을 형성하고 이 막 내에 홀을 형성하고, 이 홀을 통해 제2절연막을 건식 식각으로 제거하며, 계속하여 제1절연막를 습식 식각으로 제거하고, 제1절연막 내에 형성된 홀 형상의 크기로 제2절연막의 측면에 대해 습식 식각으로 더 제거한 후 포토레지스트막을 제거함으로써, 금속층 형성시 홀 내부에 빈 공간이 없도록 함과 아울러 금속층의 피복성을 향상한 2중 절연막의 접촉홀 형성 방법에 관한 것으로서, 또한 고내압 반도체 스위칭 파워 바이폴라 트랜지스터에 적용될 수 있는 공정이다.The present invention is formed on a semiconductor layer, forming a first insulating film and a second insulating film of sufficient thickness to withstand a high voltage, and a contact for forming a contact hole for contact between the semiconductor layer and the conductive layer In order to form the hole, a photoresist film is formed on the second insulating film, and a hole is formed in the film, through which the second insulating film is removed by dry etching, and then the first insulating film is removed by wet etching. By removing the photoresist film after wet removal of the side surface of the second insulating film to the size of the hole formed in the insulating film, there is no empty space inside the hole when forming the metal layer, and also improves the coating property of the metal layer The present invention relates to a method for forming a contact hole, and is also a process that can be applied to a high breakdown voltage semiconductor switching power bipolar transistor.

Description

이중 절연막을 갖는 반도체 장치 접촉홀 형성 방법Method for forming contact hole in semiconductor device having double insulating film

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도(a)∼제3도(e)는 본 발명에 따른 이중 절연막을 갖는 반도체 장치의 접촉홀 형성 방법을 설명하는 공정도.3A to 3E are process drawings for explaining a method for forming a contact hole in a semiconductor device having a double insulating film according to the present invention.

Claims (6)

반도체 층 상에 형성되며, 고전압에 견딜 수 있도록 충분한 두께의 제1절연막 및 이 위의 제2절연막을 형성하고, 상기 반도체 층과 도전층과의 접촉을 위한 접촉홀을 형성하기 위한 접촉홀 형성 방법에 있어서, 상기 제2절연막 상에 포토레지스트막을 형성하고 이 막 내에 상기 접촉홀 형성을 위한 홀을 형성하는 단계; 상기 홀을 통해 드러난 상기 제2절연막을 그 부분에 대해 건식 식각으로 제거하는 단계; 상기 반도체 층 표면이 노출되도록 상기 제2절연막 제거에 의해 노출된 부분에 대해 상기 제1절연막을 습식 식각하는 단계; 및 상기 제1절연막 내에 형성된 홀 형상의 크기로 상기 제2절연막의 측면에 대해 습식 식각으로 더 제거한 후 상기 포토레지스트막을 제거하는 단계를 포함하는 것을 특징으로하는 반도체 장치의 접촉홀 형성 방법.A method of forming a contact hole formed on the semiconductor layer to form a first insulating film and a second insulating film thereon of sufficient thickness to withstand high voltage, and to form a contact hole for contact between the semiconductor layer and the conductive layer; Forming a photoresist film on the second insulating film and forming a hole for forming the contact hole in the film; Removing, by dry etching, the portion of the second insulating layer exposed through the hole; Wet etching the first insulating layer with respect to the exposed portion by removing the second insulating layer so that the surface of the semiconductor layer is exposed; And removing the photoresist film after wet removal of the side surface of the second insulating film to a size of a hole shape formed in the first insulating film, and then removing the photoresist film. 제1항에 있어서, 상기 제1절연막은 산화막이며, 상기 제2절연막은 질화막인 것을 특징으로 하는 바이폴라 스위칭 파워 트랜지스터 반도체 장치의 접촉홀 형성 방법.The method of claim 1, wherein the first insulating film is an oxide film and the second insulating film is a nitride film. 반도체 바이폴라 스위칭 파워 트랜지스터의 일부를 구성하는 반도체층과, 이 반도체 층 상에 형성되며, 상기 트랜지스터에 가해지는 고전압에 견딜 수 있도록 충분한 두께의 제1절연막 및 이 위의 제2절연막, 상기 반도체 층과 상기 트랜지스터의 배선을 위한 도전층과의 접촉을 위한 접촉홀이 적어도 구비된 반도체 바이폴라 스위칭 파워 트랜지스터의 상기 접촉홀을 형성하는 방법에 있어서, 상기 제2절연막을 형성한 후 이 위에 포토레지스트막을 형성하여 이 막 내에 상기 접촉홀을 형성을 위한 홀을 형성하는 단계; 상기 홀을 통해 드러난 상기 제2절연막을 그 부분에 대해 건식 식각으로 제거하는 단계; 상기 반도체 층 표면이 노출되도록 상기 제2절연막 제거에 의해 노출된 부분에 대해 상기 제1절연막을 습식 식각하는 단계; 및 상기 제1절연막 내에 형성된 홀 형상의 크기로 상기 제2절연막 측면에 대해 습식 식각으로 더 제거한 후 상기 포토레지스트막을 제거하는 단계를 포함하는 것을 특징으로 하는 바이폴라 스위칭 파워 트랜지스터 반도체 장치의 접촉홀 형성 방법.A semiconductor layer constituting a portion of the semiconductor bipolar switching power transistor, a first insulating film formed on the semiconductor layer, and having a sufficient thickness to withstand the high voltage applied to the transistor; A method of forming the contact hole of a semiconductor bipolar switching power transistor having at least contact holes for contact with a conductive layer for wiring of the transistor, wherein the second insulating film is formed and a photoresist film is formed thereon. Forming a hole in the film for forming the contact hole; Removing, by dry etching, the portion of the second insulating layer exposed through the hole; Wet etching the first insulating layer with respect to the exposed portion by removing the second insulating layer so that the surface of the semiconductor layer is exposed; And removing the photoresist layer after wet removal of the side surface of the second insulating layer to a size of a hole shape formed in the first insulating layer, and then removing the photoresist layer. . 제2항에 있어서, 상기 제1절연막은 산화막이며, 상기 제2절연막을 질화막인 것을 특징으로 하는 바이폴라 스위칭 파워 트랜지스터 반도체 장치의 접촉홀 형성 방법.The method of claim 2, wherein the first insulating film is an oxide film and the second insulating film is a nitride film. 제1항에 있어서, 상기 반도체 장치는 15000V의 인가 전압에 견디는 고내압 소자인 것을 특징으로 하는 바이폴라 스위칭 파워 트랜지스터 반도체 장치의 접촉홀 형성 방법.2. The method of claim 1, wherein the semiconductor device is a high breakdown voltage element that withstands an applied voltage of 15000V. 제1항에 있어서, 상기 포토레지스터는 창 형성 및 제2절연막의 표면 에칭 방지를 위한 것임을 특징으로 하는 바이폴라 스위칭 파워 트랜지스터 반도체 장치의 접촉홀 형성 방법.The method of claim 1, wherein the photoresist is for forming a window and preventing surface etching of the second insulating layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950031387A 1995-09-22 1995-09-22 Method for forming contact hole of semiconductor device having double insulating layer KR100362472B1 (en)

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KR1019950031387A KR100362472B1 (en) 1995-09-22 1995-09-22 Method for forming contact hole of semiconductor device having double insulating layer

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KR100362472B1 KR100362472B1 (en) 2003-02-05

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