KR970012687A - Semiconductor Memory Device Reduces Voltage Consumption in Standby State - Google Patents

Semiconductor Memory Device Reduces Voltage Consumption in Standby State Download PDF

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Publication number
KR970012687A
KR970012687A KR1019950028400A KR19950028400A KR970012687A KR 970012687 A KR970012687 A KR 970012687A KR 1019950028400 A KR1019950028400 A KR 1019950028400A KR 19950028400 A KR19950028400 A KR 19950028400A KR 970012687 A KR970012687 A KR 970012687A
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KR
South Korea
Prior art keywords
semiconductor memory
memory device
power supply
standby state
supply voltage
Prior art date
Application number
KR1019950028400A
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Korean (ko)
Other versions
KR100197569B1 (en
Inventor
윤진득
황충열
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950028400A priority Critical patent/KR100197569B1/en
Publication of KR970012687A publication Critical patent/KR970012687A/en
Application granted granted Critical
Publication of KR100197569B1 publication Critical patent/KR100197569B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

1. 청구범위에 기재되 발명이 속하는 기술 분야1. The technical field to which the invention pertains as defined in the claims

반도체 메모리 장치에 관한 것이다.A semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

대기상태시 소비되는 전압을 줄일 수 있는 반도체 메모리 장치를 제공함에 있다.The present invention provides a semiconductor memory device capable of reducing a voltage consumed in a standby state.

3. 발명이 해결방법의 요지3. Summary of the Invention Solution

반도체 메모리 장치가 정상적인 동작을 할 때는 상기 전원전압을 상기 반도체 메모리 장치의 내부로 인가하고, 상기 반도체 메모리 장치가 대기상태시에는 상기 전원전압이 소정전압 다운된 전압을 반도체 메모리 장치의 내부로 인가하는 제어수단을 구비한다.When the semiconductor memory device is in normal operation, the power supply voltage is applied to the inside of the semiconductor memory device. When the semiconductor memory device is in the standby state, the power supply voltage is applied to the inside of the semiconductor memory device. Control means.

4. 발명의 중요한 용도4. Important uses of the invention

고집적 반도체 메모리 장치에 적합하게 사용된다.It is suitably used for highly integrated semiconductor memory devices.

Description

대기상태시 소비되는 전압을 줄인 반도체 메모리 장치Semiconductor Memory Device Reduces Voltage Consumption in Standby State

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 반도체 메모리 장치의 입력단회로도.1 is an input end circuit diagram of a semiconductor memory device according to the present invention.

Claims (3)

외부의 전원전압을 인가받는 입력단을 가지는 반도체 메모리 장치에 있어서 : 상기 반도체 메모리 장치가 정상적인 동작을 할때는 상기 전원전압을 상기 반도체 메모리 장치의 내부로 인가하고, 상기 반도체 메모리 장치가 대기 상태시에는 상기 전원전압이 소정전압 다운된 전압을 반도체 메모리 장치의 내부로 인가하는 제어 수단을 구비함을 특징으로 하는 반도체 메모리 장치.A semiconductor memory device having an input terminal for receiving an external power supply voltage, the semiconductor memory device comprising: applying the power supply voltage to the inside of the semiconductor memory device when the semiconductor memory device is in normal operation, and the power supply when the semiconductor memory device is in a standby state. And control means for applying a voltage having a predetermined voltage down to the inside of the semiconductor memory device. 제1항에 있어서, 상기 제어수단은 상기 전원전압을 인가받는 전송게이트와, 상기 전송게이트를 제어하기 위한 제어회로와, 상기 전원전압을 인가받아 전압을 다운시키기 위해 드레인-소오스간의 채널이 직렬로 접속된 트랜지스터 그룹으로 구성됨을 특징으로 하는 반도체 메모리 장치.The method of claim 1, wherein the control means comprises a transfer gate to which the power supply voltage is applied, a control circuit to control the transfer gate, and a channel between the drain and the source in order to reduce the voltage by receiving the power supply voltage in series. And a transistor group connected to the semiconductor memory device. 제2항에 있어서, 상기 트랜지스터 그룹은 적어도 한개 이상의 엔모오스 트랜지스터로 구성됨을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device of claim 2, wherein the transistor group comprises at least one enmos transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950028400A 1995-08-31 1995-08-31 Semiconductor memory device reducing spending voltage on stand-by KR100197569B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950028400A KR100197569B1 (en) 1995-08-31 1995-08-31 Semiconductor memory device reducing spending voltage on stand-by

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950028400A KR100197569B1 (en) 1995-08-31 1995-08-31 Semiconductor memory device reducing spending voltage on stand-by

Publications (2)

Publication Number Publication Date
KR970012687A true KR970012687A (en) 1997-03-29
KR100197569B1 KR100197569B1 (en) 1999-06-15

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Application Number Title Priority Date Filing Date
KR1019950028400A KR100197569B1 (en) 1995-08-31 1995-08-31 Semiconductor memory device reducing spending voltage on stand-by

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Also Published As

Publication number Publication date
KR100197569B1 (en) 1999-06-15

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