KR970008159A - Semiconductor memory device and driving voltage supply method - Google Patents

Semiconductor memory device and driving voltage supply method Download PDF

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Publication number
KR970008159A
KR970008159A KR1019950019796A KR19950019796A KR970008159A KR 970008159 A KR970008159 A KR 970008159A KR 1019950019796 A KR1019950019796 A KR 1019950019796A KR 19950019796 A KR19950019796 A KR 19950019796A KR 970008159 A KR970008159 A KR 970008159A
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South Korea
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power supply
supply voltage
peripheral circuit
switching means
memory device
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KR1019950019796A
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Korean (ko)
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KR0182962B1 (en
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심재훈
이규찬
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김광호
삼성전자 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 메모리장치에 관한 것으로, 특히 외부전원공급전압이 변화할 때 소자들에게 가해지는 스트레스 및 오작동이 최소화되도록 구동전압을 가변적으로 공급하는 반도체 메모리장치 및 그 구동전압 공급방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a driving voltage supply method for supplying a driving voltage variably so as to minimize stress and malfunction applied to elements when an external power supply voltage changes.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

기존의 반도체 메모리장치에서는 저전원전압레벨일때 보상하기 위한 전원전압의 보상수단이 사용되었으나 고전원전압상태일 때 그에 적응적인 구동전압을 공급하는 장치가 없었다.In the conventional semiconductor memory device, the compensation means of the power supply voltage for compensating at the low power supply voltage level is used, but there is no device for supplying an adaptive driving voltage in the high power supply voltage state.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

상기 과제를 해결하기 위하여 본 발명에서는 레벨감지기의 출력을 2개로 분할하고 각각의 출력을 제1스위칭수단과 제2스위칭수단으로 전달하여 선택적인 구동전압의 공급이 가능해졌다.In order to solve the above problems, in the present invention, the output of the level sensor is divided into two and the respective outputs are transferred to the first switching means and the second switching means, thereby enabling the selective supply of the driving voltage.

4. 발명의 중요한 용도4. Important uses of the invention

본 발명에 따른 반도체 메모리장치가 제공되므로써 오동작을 방지하고 반도체 메모리장치를 구성하는 소자들에게 가해지는 스트레스를 줄이는 안정적인 반도체 메모리장치가 구현된다.By providing the semiconductor memory device according to the present invention, a stable semiconductor memory device is implemented, which prevents a malfunction and reduces stress applied to elements constituting the semiconductor memory device.

Description

반도체 메모리장치 및 구동전압 공급방법Semiconductor memory device and driving voltage supply method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 실시예에 따른 전원전압의 사용상태를 나타내는 블럭도.3 is a block diagram showing a state of use of a power supply voltage according to an embodiment of the present invention.

Claims (5)

구동전압레벨에 따라 제1주변회로와 제2주변회로로 분할되는 주변회로와, 다수의 메모리정보들이 저장된 코아부와, 데이타를 칩내외부로 전송하도록 버퍼링하는 입출력버퍼와, 외부전원전압레벨을 내부전원전압레벨로 강하하여 칩내부를 구성하는 내부회로들로 전달하는 내부전원전압 발생회로를 구비하는 반도체 메모리장치에 있어서, 외부전원전압단자와 상기 입출력버퍼 및 제1주변회로 사이의 라인상에 형성되고 레벨감지기의 출력에 응답하여 도통유무가 결정되는 제1스위칭수단과, 외부전원전압이 전달되는 상기 제1주변회로 및 입출력버퍼와 내부전원전압이 전달되는 상기 제2주변회로 및 코아부를 연결하는 라인상에 형성되고 상기 레벨감지기의 출력에 응답하여 도통유무가 결정되는 제2스위칭수단과, 외부전원전압레벨을 감지하여 상기 외부전원전압레벨이 정상전원전압상태일때는 상기 제1주변회로 및 입출력버퍼를 외부전원전압으로 구동되도록 하고 상기 외부 전원전압레벨이 고전원전압상태일때는 상기 제1주변회로 및 입출력버퍼를 내부전원전압으로 구동되도록 상기 제1 및 제2스위칭수단을 제어하는 레벨감지기를 구비함을 특징으로 하는 반도체 메모리장치.A peripheral circuit divided into a first peripheral circuit and a second peripheral circuit according to the driving voltage level, a core part storing a plurality of memory informations, an input / output buffer buffering data to be transferred into and out of the chip, and an external power supply voltage level. A semiconductor memory device having an internal power supply voltage generation circuit which is lowered to a power supply voltage level and transferred to internal circuits constituting a chip, wherein the semiconductor memory device is formed on a line between an external power supply voltage terminal and the input / output buffer and the first peripheral circuit. And a first switching means for determining the conduction in response to the output of the level sensor, connecting the first peripheral circuit and the input / output buffer to which the external power voltage is transmitted, and the second peripheral circuit and the core part to which the internal power voltage are transmitted. Second switching means formed on a line and configured to determine whether conduction is in response to the output of the level sensor; When the external power supply voltage level is in the normal power supply voltage state, the first peripheral circuit and the input / output buffer are driven at an external power supply voltage. When the external power supply voltage level is in the high power supply voltage state, the first peripheral circuit and the input / output buffer are internally powered. And a level sensor for controlling the first and second switching means to be driven by a voltage. 제1항에 있어서, 상기 레벨감지기가 전원전압 디텍터임을 특징으로 하는 반도체 메모리장치.The semiconductor memory device of claim 1, wherein the level sensor is a power supply voltage detector. 제1항에 있어서, 상기 제1스위칭수단 및 제2스위칭수단이 모오스 트랜지스터임을 특징으로 하는 반도체 메모리장치.The semiconductor memory device according to claim 1, wherein the first switching means and the second switching means are MOS transistors. 소정의 전압레벨 이상의 구동전압을 입력하는 제1주변회로 및 코아부와, 상기 소정의 전압레벨 이하의 구동전압을 입력하는 제2주변회로 및 입출력버퍼와, 상기 제1주변회로 및 코아부에 내부전원전압을 공급하는 내부전원전압 발생회로와, 외부전원전압단자와 상기 입출력버퍼 및 제1주변회로 사이의 라인상에 형성되고 레벨감지기의 출력에 응답하여 도통유무가 결정되는 제1스위칭수단과, 외부전원전압이 전달되는 상기 제1주변회로 및 입출력버퍼와 내부전원전압이 전달되는 상기 제2주변회로 및 코아부를 연결하는 라인상에 형성되고 상기 레벨감지기의 출력에 응답하여 도통유무가 결정되는 제2스위칭수단을 구비하는 반도체 메모리 장치의 구동전압 공급방법에 있어서, 상기 외부전원전압레벨이 정상전원전압상태일때는 상기 제1스위칭수단을 비도통시키고 제2스위칭수단을 도통시키어 상기 제1주변회로 및 입출력버퍼에 외부전원전압이 공급되게 하는 제1방법과, 상기 외부전원전압레벨이 고전원전압상태일때는 상기 제1스위칭수단을 도통시키고 제2스위칭수단을 비도통시키어 상기 제1주변회로 및 입출력버퍼에 내부전원전압이 공급되도록 하는 제2방법으로 구동되어 고전원전압에서 반도체 메모리장치를 구성하는 소자들에게 가해지는 스트레스를 억제함을 특징으로 하는 반도체 메모리장치의 구종전압 공급방법.A first peripheral circuit and a core part for inputting a driving voltage of a predetermined voltage level or higher, a second peripheral circuit and an input / output buffer for inputting a driving voltage of a predetermined voltage level or less, and the first peripheral circuit and the core part An internal power supply voltage generation circuit for supplying a power supply voltage, first switching means formed on a line between an external power supply voltage terminal, the input / output buffer and the first peripheral circuit, and the conduction is determined in response to the output of the level sensor; A first circuit formed on a line connecting the first peripheral circuit and the input / output buffer to which an external power supply voltage is transmitted and the second peripheral circuit and the core part to which an internal power supply voltage is transmitted, and determining whether conduction is determined in response to the output of the level sensor. 2. A driving voltage supplying method for a semiconductor memory device having two switching means, wherein the first switching means when the external power supply voltage level is in a normal power supply voltage state. A first method of non-conducting and conducting a second switching means to supply an external power supply voltage to the first peripheral circuit and the input / output buffer; and conducting the first switching means when the external power supply voltage level is in a high power supply state. And a second switching means so as not to conduct the second switching means so that an internal power supply voltage is supplied to the first peripheral circuit and the input / output buffer, thereby suppressing stress applied to the elements constituting the semiconductor memory device at a high power supply voltage. Old voltage supply method of a semiconductor memory device characterized in that. 제4항에 있어서, 상기 제1스위칭수단 및 제2스위칭수단으로 모오스 트랜지스터가 사용됨을 특징으로 하는 반도체 메모리장치의 구동전압 공급방법.5. The method of claim 4, wherein a MOS transistor is used as the first switching means and the second switching means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950019796A 1995-07-06 1995-07-06 Semiconductor memory apparatus & its driving voltage supply method KR0182962B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100609994B1 (en) * 1999-07-08 2006-08-09 삼성전자주식회사 Data output circuit with low leakage current characteristic in semiconductor device
KR100650726B1 (en) * 2004-11-15 2006-11-27 주식회사 하이닉스반도체 Internal voltage supplier for memory device
KR102538817B1 (en) * 2022-11-08 2023-05-31 국방과학연구소 Manufacturing method of refractory metal lining tube using explosive welding

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101053479B1 (en) * 2009-12-02 2011-08-03 주식회사 하이닉스반도체 Semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100609994B1 (en) * 1999-07-08 2006-08-09 삼성전자주식회사 Data output circuit with low leakage current characteristic in semiconductor device
KR100650726B1 (en) * 2004-11-15 2006-11-27 주식회사 하이닉스반도체 Internal voltage supplier for memory device
KR102538817B1 (en) * 2022-11-08 2023-05-31 국방과학연구소 Manufacturing method of refractory metal lining tube using explosive welding

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