KR101053479B1 - Semiconductor devices - Google Patents

Abstract

In accordance with another aspect of the present disclosure, a semiconductor device may include: a voltage sensing circuit configured to sense a driving voltage input to an internal circuit of a semiconductor device and output a selection signal according to the result; A first selection circuit transferring an externally input signal to one of a plurality of input drivers according to the selection signal; A second selection circuit for transmitting one of the output signals of the plurality of input drivers to the internal circuit according to the selection signal; A third selection circuit transferring a signal output from the internal circuit to one of a plurality of output drivers according to the selection signal; And a fourth selection circuit which transmits one of the output signals of the plurality of output drivers to the outside according to the selection signal.

I / O driver, drive voltage

Description

Semiconductor device

The present invention relates to a semiconductor device.

In recent years, the development trend of semiconductor devices has become a trend for complex equipment with multiple functions. To do this, it is necessary to make the logic circuit and the semiconductor memory device smaller and merge into one device. In addition, while merging into a single device, it is required to realize a high operating speed at low power.

In general, a semiconductor device uses a low power supply of 3.3 V or less as a power supply for reducing power consumption and ensuring reliability thereof. Power supplied to the semiconductor device is set according to the characteristics of each semiconductor device.

Since the voltage levels at which the internal circuits operate are different for each semiconductor device, a circuit that operates according to the power supply voltage level input to the semiconductor device also needs to be configured to input / output drivers that input / output data between the semiconductor device and the outside.

Therefore, in the semiconductor device according to the embodiment of the present disclosure, in the semiconductor device having two or more input / output drivers having different driving voltages, one of the input / output drivers is automatically selected according to the driving voltage level input to the internal circuit.

In a semiconductor device according to an embodiment of the present invention,

A voltage sensing circuit sensing a driving voltage input to an internal circuit of the semiconductor device and outputting a selection signal according to the result; A first selection circuit transferring an externally input signal to one of a plurality of input drivers according to the selection signal; A second selection circuit for transmitting one of the output signals of the plurality of input drivers to the internal circuit according to the selection signal; A third selection circuit transferring a signal output from the internal circuit to one of a plurality of output drivers according to the selection signal; And a fourth selection circuit which transmits one of the output signals of the plurality of output drivers to the outside according to the selection signal.

The voltage sensing circuit outputs the selection signal at a first logic level when the driving voltage is a first voltage, and outputs the selection signal at a second logic level when the driving voltage is a second voltage. It is done.
The plurality of input drivers output a signal having the first voltage level when the input signal has a high level, and output a signal having a ground voltage level when the input signal has a low level. A first input driver; And a second input driver that outputs a signal having the second voltage level when the input signal has a high level, and outputs a signal having a ground voltage level when the input signal has a low level. do.

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The first selection circuit transfers an externally input signal to the first input driver when the selection signal is a first logic level, and externally inputs a signal that is externally input when the selection signal is a second logic level. And transmits a signal output from the first input driver to the internal circuit if the selection signal is a first logic level, and transmits the signal to the internal circuit if the selection signal is a second logic level. The signal output from the input driver is characterized in that for transmitting to the internal circuit.

The plurality of output drivers output a signal having the first voltage level when the input signal level is high level, and output a signal having a ground voltage level when the input signal level is low level. 1 output driver; And a second output driver outputting a signal having the second voltage level when the input signal has a high level, and outputting a signal having a ground voltage level when the input signal has a low level. .

The third selection circuit transfers a signal output from the internal circuit to the first output driver if the selection signal is a first logic level, and outputs a signal output from the internal circuit if the selection signal is a second logic level. And transmitting the signal output from the first output driver to the outside when the selection signal is the first logic level, and transmitting the signal to the second output driver to the outside. The signal output from the second output driver may be transmitted to the outside.

As described above, in the semiconductor device according to the embodiment of the present invention, when selecting two or more input / output drivers having different driving voltages from the semiconductor device, the driving voltage level input to the internal circuit is sensed, and according to the detected voltage level. By selecting the input / output driver, there is no need to change the metal masking for each driving voltage in the fabrication process of the semiconductor device.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 is a block diagram of a semiconductor device for explaining the present invention.

Referring to FIG. 1, the semiconductor device 100 includes an internal circuit 110, an input driver group 120, and an output driver group 130.

When the semiconductor device 100 is used as a memory device, the internal circuit 110 may include memory cells for data storage and circuits for performing a program, data read, and erase operation.

In the semiconductor device 100, the driving voltage VCCQ is fixed at 3.3V or 1.8V according to the internal circuit 110.

The input driver group 120 includes first and second input drivers 121 and 122, and the output driver group 130 includes first and second output drivers 131 and 132.

The first input driver 121 outputs 3.3V when data input to the semiconductor device 100 is '1', and outputs a ground voltage when '0'.

The voltage output by the first input driver 121 is input to the internal circuit 110.

Data input to the electronic device as well as the semiconductor device 100 is digital data composed of two values, '1' and '0'. When the digital data is input, the first input driver 120 once again transmits '1' data to the driving voltage VCCQ of the internal circuit 110 in order to prevent data loss during the transfer to the internal circuit 110. Pull up to level, and '0' data pull down to ground voltage level.

The second input driver 122 operates similarly to the first input driver 121. However, when the input data is '1', the second input driver 122 outputs 1.8V.

The first output driver 131 outputs 3.3V when the data input from the internal circuit 110 is '1', and outputs a ground voltage when '0'.

The output of the first output driver 131 is output to the outside of the semiconductor device 100.

The second output driver 132 outputs 1.8V when the data input from the internal circuit 110 is '1', and outputs a ground voltage when '0' is input.

As described above, the semiconductor device 100 may include the first or second input drivers 121 and 122 and the first or second output driver according to which driving voltage VCCQ is used by the internal circuit 110. 131, 132).

That is, in the semiconductor device 100 as shown in FIG. 1, the first or second input driver 121 and 122 and the first or second output driver may be changed according to the driving voltage VCCQ of the internal circuit 110. Metal lines for connecting the 131 and 132 and the internal circuit 110 should be connected.

To this end, a driving voltage VCCQ in which the internal circuit 110 operates is stored in the manufacturing process of the semiconductor device 100, and the first or second input drivers 121 and 122 are formed using a metal mask. ) And first or second output drivers 131, 132 to the internal circuit 110. That is, the metal masking should be separately performed and managed according to the driving voltage VCCQ of the internal circuit 110.

For example, if the driving voltage VCCQ of the internal circuit 110 is 3.3V, the metal mask is made to connect the line L1 and the line L2 and the line L5 and the line L6. When the masking operation is completed, the lines L1, L2, L5, and L6 are connected.

Accordingly, the first input driver 121 and the first output driver 131 are connected to the 3.3V which is the driving voltage VCCQ of the internal circuit 110 of the semiconductor device 100.

As described above, the method of connecting the input / output driver to the internal circuit by separately performing metal masking according to the operating voltage continuously monitors the driving voltage VCCQ of the internal circuit 110 during the manufacturing process of the semiconductor device 100. After the manufacturing is completed, the information on the driving voltage VCCQ has to be managed separately.

In the exemplary embodiment of the present invention, a semiconductor device for performing one metal masking operation without performing different metal masking operations for each driving voltage and automatically selecting an input / output driver according to a voltage driven by an internal circuit will be described. .

2 is a block diagram of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, the semiconductor device 200 according to an embodiment of the present invention includes an internal circuit 210, an input driver block 220, an output driver block 230, and a voltage sensing circuit 240.

The internal circuit 210 of the semiconductor device 200 according to the embodiment of the present invention is fixed to a driving voltage VCCQ of 3.3 V or 1.8 V. The internal circuit 210 according to the embodiment of the present invention is driven. Assume that the voltage VCCQ is 3.3V.

When the semiconductor device 200 is a memory device, the internal circuit 210 programs memory cells for data storage, data in the memory cell, read data programmed in the memory cell, or the memory cell. Peripheral circuitry for erasing the data.

The internal circuit 210 outputs control signals SET and REF for controlling the operation of the voltage sensing circuit 240.

The input driver block 220 includes first and second input drivers 221 and 222 and first and second selection circuits 223 and 224, and the output driver block 230 includes first and second output drivers. 231 and 232 and third and fourth selection circuits 233 and 234.

The first input driver 221 outputs 3.3V when the data transmitted from the first selection circuit 223 is '1' and outputs a ground voltage when '0'.

The output of the first input driver 221 is input to the second selection circuit 224.

The second input driver 222 outputs 1.8V when the data transmitted from the first selection circuit 223 is '1' and outputs a ground voltage when '0'. The output of the second input driver 222 is also input to the second selection circuit 224.

The first selection circuit 223 receives data input from the outside of the semiconductor device 200 in response to a selection signal provided by the voltage sensing circuit 240. To pass).

The second selection circuit 224 transfers data transferred from the first input driver 221 to the internal circuit 210 or internally transfers data transferred from the second input driver 222 according to the selection signal Select. Transfer to circuit 210.

The first output driver 231 outputs 3.3V when the data transmitted from the third selection circuit 233 is '1', and outputs a ground voltage when '0'.

The output of the first output driver 231 is input to the fourth selection circuit 234.

The second output driver 232 outputs 1.8V when the data transmitted from the third selection circuit 233 is '1' and outputs a ground voltage when '0'. The output of the second output driver 232 is also input to the fourth selection circuit 234.

The third selection circuit 233 transfers the data output from the internal circuit 210 to the first output driver 231 or the second output driver 232 according to the selection signal Select.

The fourth selection circuit 234 selects one of the first output driver 231 or the second output driver 232 according to the selection signal Select to select the first or second output driver 231 or 232. The data transferred from the data is transferred to the outside of the semiconductor device 200.

When the first and second input drivers 221 and 222 and the first and second output drivers 231 and 232 input data according to respective driving voltages VCCQ = 3.3V or 1.8V, '1'. The driver pulls up to 3.3V or 1.8V and outputs it by pulling down the ground voltage if it is '0'.

The voltage sensing circuit 240 senses a voltage level of the driving voltage VCCQ input from the semiconductor device 200 according to the control signals SET and REF input from the internal circuit 210, and detects a voltage level of the detected voltage level. Outputs a selection signal (Select).

3 illustrates the first selection circuit of FIG. 2.

Referring to FIG. 3, the first selection circuit 223 includes a first NMOS transistor N1 and a first PMOS transistor P1.

The first NMOS transistor N1 is connected between an input terminal through which data is input from the outside and an input terminal of the first input driver 221. The first PMOS transistor P1 is connected to an input terminal and a second input driver through which data is input from the outside. Is connected between the input terminals of 222.

The select signal Select is commonly input to the gates of the first NMOS transistor N1 and the first PMOS transistor P1.

Therefore, when the select signal Select is at a high level, the first select circuit 223 transmits data input from the outside to the first input driver 221 when the first NMOS transistor N1 is turned on.

When the select signal Select is at a low level, the first PMOS transistor P1 is turned on to transmit data input from the outside to the second input driver 222.

The second to fourth selection circuits 224, 233, and 234 also have the same circuit configuration as the first selection circuit 223.

In addition, the voltage sensing circuit 240 may be configured using known voltage sensing circuits to output a select signal in accordance with the voltage level of the driving voltage VCCQ.

For example, the voltage sensing circuit 240 may be configured of the following circuit.

4 illustrates the voltage sensing circuit of FIG. 2.

Referring to FIG. 4, the voltage sensing circuit 240 includes an external voltage sensing circuit 241 and an output logic circuit 242.

The external voltage sensing circuit 241 includes second to fourth PMOS transistors P2 to P4 and second to third NMOS transistors N2 to N3.

The driving voltage VCCQ is input to the source of the second PMOS transistor P2, and the drain thereof is connected to the node D1. The gate of the second PMOS transistor P2 is connected to the node D2.

Gates of the third and fourth PMOS transistors P3 and P4 are connected to the node D1, and the driving voltage VCCQ is input to a source of the third PMOS transistor P3. The drain of the third PMOS transistor P3 is connected to the source of the fourth PMOS transistor P4. A drain of the fourth PMOS transistor P4 is connected to the node D2.

The drain and gate of the second NMOS transistor N2 are connected to the node D1, and the source thereof is connected to ground. According to the operation of the second PMOS transistor P2 and the second NMOS transistor N2, the voltage level of the node D1 is changed.

A drain of the third NMOS transistor N3 is connected to the node D2, and a control signal SET is input to the gate of the third NMOS transistor N3. The drain of the third NMOS transistor N3 is connected to ground. The control signals SET and REF are input from the internal circuit 210.

In response to the control signals SET and REF, the voltage sensing circuit 240 operates the node P as the third PMOS transistor P3, the fourth PMOS transistor P4, and the third NMOS transistor N3 operate. The voltage level of D2) is changed.

The output logic circuit 242 may be implemented with the first to third inverters 243, 245, and 246 and the NOR gate 244. The first inverter 243 inverts and outputs the voltage level of the node D2, and the NOR gate 244 responds to the output signal and the control signal REF of the first inverter 243, thereby providing a logic signal ( Output G). The control signal REF is set at a low level. The second inverter 245 inverts the logic signal G, and the inverted signal third inverter 246 inverts it again and outputs it as a select signal.

The operation of the voltage sensing circuit 240 is as follows.

When power is input to the semiconductor device 200, the internal circuit 210 starts driving and outputs the control signal SET to a high level for a predetermined time, and then changes the output to a low level. A third NMOS transistor while at a high level in the control signal SET

Since N3 is turned on, node D2 is at a low level. When the node D2 is at the low level, the second PMOS transistor P2 is turned on.

When the second PMOS transistor P2 is turned on, as the driving voltage VCCQ increases, the voltage of the node D1 increases. When the voltage of the node D1 reaches a set voltage, the second NMOS transistor N2 is turned on.

When the voltage of the node D1 is smaller than the set voltage, the second NMOS transistor N2 is maintained in the turned off state.

In this case, the second NMOS transistor N2 is designed to be turned on when the driving voltage VCCQ is applied at 3.3V and to be turned off when the driving voltage VCCQ is 1.8V.

That is, when the driving voltage VCCQ is applied at 3.3V, the second NMOS transistor N2 is turned on. When the second NMOS transistor N2 is turned on, the node D1 is at a low level.

When the node D1 is at the low level, the third and fourth PMOS transistors P3 and P4 are turned on.

On the other hand, as described above, the control signal SET is at a high level only at a set time and is at a low level thereafter. Therefore, when the control signal SET is changed to the low level while the third and fourth PMOS transistors P3 and P4 are turned on, when the third NMOS transistor N3 is turned off, the third and fourth nodes are connected to the node D2. The driving voltage VCCQ is applied through the 4 PMOS transistors P3 and P4. In other words, the voltage level of the node D2 becomes high.

Thereafter, the first inverter 243 inverts the high level voltage state of the node D2 and outputs the low level. The output of the first inverter 243 is input to the NOR gate 244.

The control signal REF input to the NOR gate 244 is always at a low level.

Therefore, the NOR gate 244 outputs a high level logic signal G.

The logic signal G is inverted through the second inverter 245 and inverted again through the third inverter 246. The third inverter 246 outputs a high level select signal Select.

Therefore, when the driving voltage VCCQ is applied at 3.3V, the select signal Select is output at a high level.

If the driving voltage VCCQ is applied at 1.8V, the second NMOS transistor N2 is maintained in the turned off state.

Therefore, the node D1 is maintained at the high level, and the third and fourth PMOS transistors P3 and P4 also remain turned off.

As a result, the node D2 remains at a low level while the control signal SET is initially input at a high level. Therefore, the selection signal Select is finally output at the low level.

The voltage sensing circuit 240 as described above is an embodiment, and various voltage sensing circuits currently known may be applied.

The operation of the semiconductor device 200 will now be described in detail.

First, as previously assumed, the driving voltage VCCQ of the internal circuit 210 of the semiconductor device 200 is set to 3.3 V, and the driving voltage VCCQ is input to drive the semiconductor device 200.

The voltage sensing circuit 240 senses the voltage level of the driving voltage VCCQ while the semiconductor device 200 starts to drive. Since the driving voltage VCCQ of 3.3V is input to the semiconductor device 200 according to the embodiment, the voltage sensing circuit 240 outputs a high level select signal Select. If the driving voltage VCCQ is 1.8V, the voltage sensing circuit 240 outputs a low level select signal Select. Of course, it is also possible to reverse the select signal (Select) output when the 3.3V and 1.8V.

Data that drives the semiconductor device 200 to be driven is input from external devices connected to the semiconductor device 200. The external devices are devices that can operate in connection with the semiconductor device 200. If the semiconductor device 200 is a memory device, the external devices may be PCs, mobile phones, and the like, which store data using the memory device.

Meanwhile, data input from an external device is input to the first selection circuit 223.

The first selection circuit 223 transfers externally input data to the first or second input driver 221 or 222 according to the selection signal Select.

Since the selection signal Select is input at a high level, the first selection circuit 223 transfers the signal to the first input driver 221. If the select signal Select is at the low level, the first select circuit 223 transfers externally input data to the second input driver 222.

The first selection circuit 223 may be configured as a switching element for transferring data input from the outside to the first or second input driver 221 or 222 according to the selection signal Select. That is, when the selection signal Select is input at a high level, the switching element connecting the input terminal to which the data is input from the outside and the first input driver 221 is turned on, and when the selection signal Select is input at the low level, data from the outside is input. The circuit may be configured such that a switching element connecting the input terminal to which the input signal is input and the second input driver 222 is turned on.

In this case, the first selection circuit 223 connects only one of the first or second input drivers 221 and 222 to an input terminal for data input, and simultaneously connects the first and second input drivers 221 and 222 and the input terminal. Do not connect.

When the selection signal Select is input at a high level and the first input driver 221 receives externally input data, the first input driver 221 receives data transmitted through the first selection circuit 223. '1' data is pulled up to 3.3V and '0' data is pulled down to ground voltage and output.

To this end, the first input driver 221 has a circuit configuration to have a function to pull up or pull down the data input to '1' or '0' and output to 3.3V when the data is pulled up. It should be possible. Similarly, the second input driver 222 is configured to pull up the '1' data to 1.8V and output the '0' data to the ground voltage.

The second selection circuit 224 is similar in configuration to the first selection circuit 223. When the selection signal (Select) is input at a high level, the second selection circuit 224 outputs the data of the first input driver 221 so that data output from the first input driver 221 is transferred to the internal circuit 210. And the internal circuit 210 connect the data input terminal.

In addition, when the selection signal Select is input at a low level, the second selection circuit 224 connects the data output terminal of the second input driver 222 and the data input terminal of the internal circuit 210. The second selection circuit 224 may also be configured with a switching element similar to the first selection circuit 223.

The internal circuit 210 of the semiconductor device 200 according to an embodiment of the present invention uses 3.3V as the driving voltage VCCQ and outputs the first input driver 221 by the second selection circuit 224. Receive data.

The externally input data includes an operation command and address information for instructing the operation of the internal circuit 210. Accordingly, the internal circuit 210 performs an operation according to the operation command. The data is output again to the outside according to the operation result.

Operation result data output from the internal circuit 210 is input to the third selection circuit 223.

When the select signal Select is input at a high level, the third select circuit 223 transfers the result data output from the internal circuit 210 to the first output driver 231, and the select signal Select is at a low level. When input as, the result data output from the internal circuit 210 is transferred to the second output driver 232.

The internal circuit 210 of the semiconductor device 200 according to the embodiment of the present invention uses 3.3V as the driving voltage VCCQ, and the voltage sensing circuit 240 senses the driving voltage VCCQ as 3.3V to make it high. Since the level selection signal Select is output, the third selection circuit 233 transfers the result data output from the internal circuit 210 to the first output driver 231.

The first output driver 231 pulls up the '1' data to 3.3V from the result data output from the internal circuit 210 and outputs the '0' data down to the ground voltage.

The output of the first output driver 231 is transmitted to the fourth selection circuit 234.

Similar to the third selection circuit, the fourth selection circuit 234 outputs data output from the first output driver 231 to an external device because the selection signal Select is at a high level.

The first to fourth selection circuits 223, 224, 233, and 234 and the voltage sensing circuit 240 may be configured in other embodiments as follows.

5 illustrates another embodiment of the first selection circuit of FIG. 2.

Referring to FIG. 5, the first selection circuit 223 according to another embodiment may include the fourth and fifth NMOS transistors N4 and N5, the fifth and sixth PMOS transistors P5 and P6, and the first to third inverters ( IN1 to IN3).

The fourth NMOS transistor N4 and the fifth PMOS transistor P5 are composed of one switch circuit connected between the data input terminal and the first input driver 221 from the outside, and the fifth NMOS transistor N5 and the sixth. The PMOS transistor P6 is composed of another switching circuit connected between the data input terminal from the outside and the second input driver 222.

The select signal Select from the voltage sensing circuit 240 is input to the node K2. Node K2 is connected to the gate of sixth PMOS transistor P6.

The third inverter IN3 inverts and outputs the selection signal Select input to the node K2. The output of the third inverter IN3 is input to the gate of the fifth NMOS transistor N5.

The second inverter IN2 also inverts and outputs the selection signal Select input to the node K2. The output of the second inverter IN2 is input to the node K1.

Node K1 is connected to the gate of fifth PMOS transistor P5.

The first inverter IN1 inverts and outputs a signal input to the node K1. The output of the first inverter IN1 is input to the gate of the fourth NMOS transistor N4.

If the selection signal Select is at the high level according to the circuit configuration described above, the node K2 is at the high level. When the node K2 is at the high level, the sixth PMOS transistor P6 is turned off.

The output of the third inverter IN3 is at the low level. If the output of the third inverter IN3 is at the low level, the fourth NMOS transistor N4 is also turned off.

The output of the second inverter IN2 also becomes a low level. Therefore, the node K1 is at a low level.

When the node K1 is at the low level, the fifth PMOS transistor P5 is turned on.

When the node K1 is at the low level, the output of the first inverter IN1 is at the high level.

If the output of the first inverter IN1 is at a high level, the fourth NMOS transistor N4 is turned off.

The fourth NMOS transistor N4 and the fifth PMOS transistor P5 are turned on, and the fifth NMOS transistor N5 and the sixth PMOS transistor P6 are turned off.

Therefore, when the select signal Select is at a high level, data from the outside is transmitted to the first input driver 221.

In contrast, when the select signal Select is input at a low level, only the fifth NMOS transistor N5 and the sixth PMOS transistor P6 are turned on. Therefore, when the select signal Select is at the low level, data from the outside is transferred to the second input driver 222.

On the other hand, the voltage sensing circuit 240 may be configured in another embodiment different from FIG. 4.

6 illustrates another embodiment of the voltage sensing circuit of FIG. 2.

Referring to FIG. 6, the voltage sensing circuit 240 according to another embodiment includes a reference voltage generating circuit 247, a comparator COMP, and first and second resistors R1 and R2.

The reference voltage generator 247 outputs a reference voltage Vref of about 2.3V. Since the reference voltage generation circuit 247 has many known circuits, the configuration of the circuit is omitted.

The reference voltage Vref is input to the inverting terminal (-) of the comparator COMP.

The first and second resistors R1 and R2 are connected in series between the driving voltage VCCQ and the ground node, and the distribution voltage from the node K3, which is a connection point of the first and second resistors R1 and R2, is connected. It is input to the non-inverting terminal + of this comparator COMP.

The comparator COMP outputs a high level select signal Select when the voltage of the node K3 input to the inverting terminal + is higher than the voltage of the reference voltage Vref input to the non-inverting terminal (-). When the voltage of the node K3 input to the inverting terminal + is lower than the voltage of the reference voltage Vref input to the non-inverting terminal (−), a low level select signal Select is output.

Therefore, assuming that the voltage of the node K3 is aV when the driving voltage is 3.3V, and the voltage of the node K3 is bV when the driving voltage is 1.8V, the reference voltage Vref is lower than aV. Maintain a higher voltage level than bV.

When configuring the voltage sensing circuit 240 as shown in FIG. 6, the control signals SET and REF from the internal circuit 210 may not be input. However, a control signal (not shown) for controlling the operation of the reference voltage generation circuit 247 may be input.

The semiconductor device 200 according to the embodiment of the present invention operating as described above does not need to manage voltage level information of the driving voltage VCCQ in which the internal circuit 210 operates separately during the manufacturing process, and automatically detects the voltage. The circuit 240 selects an input / output driver.

Therefore, only one metal line generation process is performed on the lines L10, L20, L30, and L40 shown in FIG. 2 without the need for masking according to the driving voltage.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 is a block diagram illustrating a semiconductor device in which data input / output drivers are connected by metal masking according to an embodiment.

2 is a block diagram of a semiconductor device according to an embodiment of the present invention.

3 illustrates the first selection circuit of FIG. 2.

4 illustrates the voltage sensing circuit of FIG. 2.

5 illustrates another embodiment of the first selection circuit of FIG. 2.

6 illustrates another embodiment of the voltage sensing circuit of FIG. 2.

* Brief description of the main parts of the drawings *

200: semiconductor device 210: internal circuit

220: input driver block 230: output driver block

240: voltage sensing circuit

Claims (12)

A voltage sensing circuit sensing a driving voltage input to an internal circuit of the semiconductor device and outputting a selection signal according to the result; A first selection circuit transferring an externally input signal to one of a plurality of input drivers according to the selection signal; A second selection circuit for transmitting one of the output signals of the plurality of input drivers to the internal circuit according to the selection signal; A third selection circuit transferring a signal output from the internal circuit to one of a plurality of output drivers according to the selection signal; And And a fourth selection circuit which transmits one of the output signals of the plurality of output drivers to the outside according to the selection signal. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Each of the plurality of input drivers and the plurality of output drivers, If the level of the input signal is a high level, it outputs a signal having its own drive voltage level, And outputting a signal having a ground voltage level if the input signal has a low level. delete delete delete Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The voltage sensing circuit, And when the driving voltage is a first voltage, output the selection signal at a first logic level, and output the selection signal at a second logic level when the driving voltage is a second voltage. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, The plurality of input drivers, A first input driver for outputting a signal having the first voltage level when the input signal level is high level, and outputting a signal having a ground voltage level when the input signal level is low level; And And a second input driver outputting a signal having the second voltage level when the input signal level is high level, and outputting a signal having a ground voltage level when the input signal level is low level. Semiconductor device. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The first selection circuit, When the selection signal is the first logic level, an externally input signal is transmitted to the first input driver. And when the selection signal is at the second logic level, transferring an externally input signal to the second input driver. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 7, wherein The second selection circuit, When the selection signal is the first logic level, a signal output from the first input driver is transmitted to the internal circuit. And transmitting the signal output from the second input driver to the internal circuit if the selection signal is at the second logic level. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 6, The plurality of output drivers, A first output driver outputting a signal having the first voltage level when the input signal level is high level, and outputting a signal having a ground voltage level when the input signal level is low level; And A semiconductor including a second output driver outputting a signal having the second voltage level when the input signal has a high level, and outputting a signal having a ground voltage level when the input signal has a low level; Device. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, The third selection circuit, If the selection signal is the first logic level, the signal output from the internal circuit is transmitted to the first output driver, And transmitting the signal output from the internal circuit to the second output driver when the selection signal is at the second logic level. Claim 12 was abandoned upon payment of a registration fee. The method of claim 10, The fourth selection circuit, If the selection signal is the first logic level, the signal output from the first output driver is transmitted to the outside, And when the selection signal is at the second logic level, transferring the signal output from the second output driver to the outside.

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