KR101456027B1 - Negative voltage supply device - Google Patents

Abstract

A first charging unit having a first end receiving a clock signal and the second end selectively connected to a ground terminal or an output terminal of the negative voltage supply unit in accordance with the clock signal, And the other end is grounded.

Description

[0001] NEGATIVE VOLTAGE SUPPLY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a negative voltage supply apparatus, and more particularly, to an apparatus for supplying a negative voltage using a differential clock signal.

In order to meet high-speed system requirements such as high-speed digital communication, high-definition high-speed display, and high-capacity storage device, the analog and digital blocks in the system are plural Are developed in the direction of using the power supply voltage of the number of

However, in some semiconductor devices or some circuits inside the semiconductor device, there are those that require a negative voltage due to their operation characteristics, so that they may be used in the same way as a semiconductor device requiring a negative voltage, There is a need for a negative voltage supply device that generates a negative voltage lower than the power supply voltage in the semiconductor device.

To supply such a negative voltage, a so-called negative voltage charge pump (NVCP) is required. The charge pump circuit utilizes the principle of charging a capacitor to a capacitor in the initial state and then transferring the charge to the capacitive load of the output terminal by using the charge conservation law to obtain a desired voltage.

Korean Patent Laid-Open Publication No. 10-2008-0063885 (published on July 8, 2008)

SUMMARY OF THE INVENTION The present invention has been made to solve all the problems of the prior art described above.

It is another object of the present invention to provide a negative voltage supply device which solves all the problems of the conventional negative voltage supply device and can only take advantage of the negative voltage supply device.

The negative voltage supplying apparatus of the present invention includes a first charging unit having one end receiving a clock signal and the other end selectively connected to a ground terminal or an output terminal of the negative voltage supplying apparatus in accordance with the clock signal, And the other end is grounded.

According to an embodiment of the present invention, there is provided a switching regulator including a first switching unit inserted between the other end of the first charging unit and the ground terminal, a second switching unit inserted between the other end of the first charging unit and the output terminal, And a bootstrap unit for providing an on / off control signal to the first switching unit and the second switching unit by strapping.

According to an embodiment of the present invention, the apparatus further includes a third switching unit inserted between the bootstrap unit and the ground terminal, and a fourth switching unit inserted between the bootstrap unit and the output terminal, 4 on / off of the switching unit can be controlled by the voltage signal of the first charging unit.

According to an embodiment of the present invention, the bootstrap unit includes a first capacitor inserted between an input terminal of the inverted clock signal and a control signal input terminal of the first switching unit, and a second capacitor connected between the input terminal of the inverted clock signal and the control signal input terminal of the second switching unit And a second capacitor which is inserted into the second capacitor.

According to an embodiment of the present invention, the first charge / discharge unit is connected to the ground terminal when the clock signal is a high (H) signal and is connected to the second charge / discharge unit when the clock signal is a low (L) The charge / discharge unit is connected to the control signal input terminal of the second switching unit when the clock signal is a high (H) signal, and can be charged when the clock signal is a low (L) signal.

According to an embodiment, at least one of the first switching unit and the third switching unit includes a P-type transistor, and at least one of the second switching unit and the fourth switching unit may include an N-type transistor .

According to the embodiment of the present invention, the negative voltage supply device can provide a negative voltage supply device which can operate through a simple circuit without using a complicated circuit configuration by using NMOS and PMOS switching transistors.

According to the embodiment of the present invention, in constructing the negative voltage supply device, it is possible to implement a simple circuit, thereby making it possible to miniaturize the product and to save manufacturing cost.

FIG. 1 is a simplified diagram showing a general negative voltage supply device.
2 is a circuit diagram showing a negative voltage supply device according to an embodiment of the present invention.
3A and 3B are circuit diagrams respectively showing charging and pumping operations of the negative voltage supply device.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

Before describing the negative voltage supply device according to the embodiment of the present invention, when the positive voltage applied to the transistor in relation to the voltage signal applied to the transistor is VDD, a high (H) signal is about VDD / 2 And a low (L) signal means a signal having a ground level of 0 V or more and less than or equal to about VDD / 2. The reference for dividing the voltage signal into a high (H) signal and a low (L) signal need not be fixed. The negative voltage supplying device and the negative voltage supplying device according to the embodiment of the present invention such as the magnitude of the applied positive voltage VDD, May vary depending on the implementation environment of the voltage level converter. That is, in the present specification, the "H" signal and the "L" signal do not refer to a signal having a certain specific value but, as a relative concept, "H" If it is a lower signal, it should be understood as a " low (L) signal ".

[Preferred Embodiment of the Present Invention]

Before describing the negative voltage supply device according to the embodiment of the present invention, the principle of a general negative voltage supply device will be briefly described.

1 is a view schematically showing the principle of a conventional negative voltage supply device.

1, a conventional negative voltage supply device includes a first switching device S1 having one end connected to a power source, a first capacitor C1 having one end connected to the other end of the first switching device S1, A second switching device S2 having one end connected to the other terminal of the first capacitor C1 and the other end connected to the ground, a third switching device S3 connected to one terminal of the first capacitor C1 and the ground, A fourth switching element S4 whose both ends are connected to the other terminal and the output terminal of the first capacitor C1, and a second capacitor C2 connected between the output terminal and the ground.

The negative voltage supply device turns on the first and second switching devices S1 and S2 to charge the first capacitor C1 to the input voltage Vin and then turns on the first and second switching devices S1 and S2 The third and fourth switching elements S3 and S4 are turned on to charge the second capacitor C2. At this time, the output voltage Vout becomes -Vin.

In FIG. 1, the first switching device S1 may be implemented as a PMOS because the input voltage Vin has a positive voltage, and the third switching device S3 may be turned on / off around the ground. So it can be easily implemented by NMOS.

Assuming that the second switching element S2 is implemented by PMOS, the off state can be achieved by grounding the gate of the PMOS, but a negative power source, that is, a negative voltage is required in order to make the on state. The output voltage Vout may be used. However, in this case, a problem may occur at the time of initial start-up.

When the second switching device S2 is implemented as an NMOS, the on state is easily realized. However, when the first switching device S1 is turned off and the third switching device S3 is turned on, the first capacitor C1, A voltage is applied to the negative terminal of the first capacitor C1 in order to turn off the second switching element S2. This makes the circuit more complex.

In the case of the fourth switching device S4, it is impossible to implement the PMOS, but it is necessary to implement the NMOS, but a circuit for making the ON / OFF state is required. This also complicates the construction of the circuit, so that it can not meet the trend of miniaturization of the product, and additional cost is incurred.

Hereinafter, a negative voltage supplying apparatus according to an embodiment of the present invention will be described in order to solve all of these problems.

2 shows a negative voltage supply device according to an embodiment of the present invention.

2, a negative voltage supplying apparatus according to an embodiment of the present invention receives a clock signal CLK at one end thereof and an output terminal 30 of the negative voltage supplying apparatus according to the clock signal CLK at the other end thereof. And a second charging unit 120 connected to the output terminal 30 at one end and grounded at the other terminal.

 2, the negative voltage supply device according to the embodiment of the present invention includes a first charging unit 110 and a ground terminal, a first charging unit 110 and an output terminal 30 for selectively connecting the charging unit 110 and the output stage 30 The first switching unit 101 and the second switching unit 101 bootstrap the first switching unit 101, the second switching unit 102, the third switching unit 103, the fourth switching unit 104 and the inverted clock signal CLK_inv, And a bootstrap unit 130 for controlling the on / off operation of the second switching unit 102.

The negative voltage supply device according to the embodiment of the present invention includes a first switching unit 101 having one end connected to the other end of the first charging unit 110 and the other end grounded, A third switching unit 103 connected to one end of the bootstrap unit 130 and grounded at the other end, a second switching unit 102 connected to the other end of the bootstrap unit 130, And a fourth switching unit 104 connected to the other end of the bootstrap unit 130 and the other end connected to the output terminal 30. [ One end of the second charge / discharge unit 120 may be connected to the output terminal 30 and the other end may be grounded.

In this case, when a node to which the other end of the first charging unit 110, one end of the first switching unit 101 and one end of the second switching unit 102 are connected is referred to as a first node N1, The voltage signal of the first node N1 is bootstrapped according to the clock signal so that it can control on / off of the third switching unit 103 and the fourth switching unit 104. When a node to which the one end of the bootstrap unit 130 is connected is referred to as a second node N2, the voltage signal of the second node N2 is connected to the first switching unit 103, The ON / OFF of the unit 101 can be controlled. When a node to which the other end of the bootstrap unit 130 is connected is referred to as a third node N3, the voltage signal of the third node N3 is input to the second switching unit 102 can be controlled on / off.

That is, the on / off of the third switching unit 103 and the fourth switching unit 104 is determined by the voltage signal of the first node N1, and the on / off of the first switching unit 101 is determined by the second And the on / off state of the second switching unit 102 may be determined by the voltage signal of the third node N3.

The first switching transistor M1 is a first switching transistor, the second switching transistor 102 is a second switching transistor M2, the third switching transistor 103 is a third switching transistor M3, The switching unit 104 may include a fourth switching transistor M4 and the first charging unit 110 may include a first capacitor C1 and the second charging unit 120 may include a second capacitor C2. can do. The first switching unit 101 and the third switching unit 103 may be P-type transistors, and the second switching unit 102 and the fourth switching unit 104 may be N-type transistors.

The bootstrap unit 130 includes a third capacitor C3 inserted between the inverted clock input terminal 20 and the second node N2 and a third capacitor C3 inserted between the inverted clock input terminal 20 and the third node N3 And a fourth capacitor C4. The third capacitor C3 receives the inverted clock signal CLK_inv from the inverted clock input terminal 20 to bootstrap the voltage of the second node N2 and the fourth capacitor C4 receives the inverted clock signal CLK_inv from the inverted clock input terminal 20 And receives the inverted clock signal CLK_inv to bootstrap the voltage of the third node N2. The voltage signal of the second node N2 and the voltage signal of the third node N3 control ON / OFF of the first switching unit 101 and the second switching unit 102.

Next, with reference to FIG. 2, a connection relationship between respective configurations of the negative voltage supply device according to an embodiment of the present invention will be described.

One end of the first capacitor C1 receives the clock voltage CLK and the other end thereof is connected to the first node N1.

The drain terminal of the first switching transistor M1 may be connected to the first node N1, the source terminal may be grounded, and the gate terminal may be connected to the second node N2. The source terminal of the second switching transistor M2 is connected to the first node N1 and the drain terminal thereof is connected to one end of the second capacitor C2 which is the output terminal 30. The gate terminal is connected to the third node N3, Lt; / RTI > The drain terminal of the third switching transistor M3 is connected to the second node N2, the source terminal is grounded, and the gate terminal may be connected to the first node N1. The drain terminal of the fourth switching transistor M4 is connected to the second node N2 and the source terminal thereof is connected to one end of the second capacitor C2 which is the output terminal 30. The gate terminal is connected to the first node N1, Lt; / RTI >

One end of the second capacitor C2 may be connected to the drain terminal of the second switching transistor M2 and the source terminal of the fourth switching transistor M4 as an output terminal 30 and the other terminal may be grounded.

The other end of the first capacitor C1 is connected to the drain terminal of the first switching transistor M1 and the source terminal of the second switching transistor M2 are connected to the first node N1, The gate terminal of the switching transistor Ml, the drain terminal of the third switching transistor M3, and the third capacitor C3 are connected. The third node N3 is connected to the gate terminal of the second switching transistor M2, the drain terminal of the fourth switching transistor M4, and the fourth capacitor C4.

Hereinafter, the charging and pumping operations of the negative voltage supply device will be described in detail.

Figs. 3A and 3B show charging and pumping operations of the negative voltage supply device of Fig. 2, respectively.

The charging principle of the first capacitor C1 will be described with reference to FIG.

A state where a positive voltage (VDD) signal as a high (H) signal is input to the clock input terminal 10 and a 0V signal as a low (L) signal is input to the inverted clock input terminal 20 is referred to as a first state, A state in which a low (L) signal of 0V is input to the input terminal 10 and a positive voltage (VDD) signal of a high (H) signal is input to the inverted clock input terminal 20 is referred to as a second state.

In the first state, a positive voltage (VDD) signal is applied to the first capacitor C1 as a clock voltage signal CLK and an inverted clock voltage signal CLK_inv is applied to the inverted clock input terminal 20, A 0V signal which is a low (L) signal is input. Assuming that the negative voltage supply device operates in a steady state, the output voltage Vout of the output stage 30 outputs a negative voltage signal. The negative voltage signal may be a negative voltage signal having the same magnitude as a positive voltage (VDD) signal corresponding to a high (H) signal applied as a clock voltage signal CLK.

In the first state, the voltage of the second node N2 is negative due to the bootstrap of the third capacitor C3. Accordingly, since the first switching transistor Ml is turned on, the first node N1 is applied with a ground signal to become a low (L) signal, and the first capacitor C1 is charged. At this time, a low (L) signal of the first node N1 is input to the gate terminals of the third switching transistor M3 and the fourth switching transistor M4. Thus, the third switching transistor M3 is turned off and the fourth switching transistor M4 is turned on. The fourth switching transistor M4 is turned on so that the voltage of the third node N3 becomes a negative voltage and the gate voltage of the second switching transistor M2 becomes a negative voltage so that the second switching transistor M2 is turned off do. As a result, in the first state in which the first capacitor C1 is charged, the first switching transistor Ml and the fourth switching transistor M4 are turned on and the second switching transistor M2 and the third switching transistor M3 are turned on Off.

Next, referring to FIG. 3B, the operation in which the first capacitor C1 is discharged and the second capacitor C2 is charged will be described.

In the second state, a 0V signal as a low (L) signal is applied to the first capacitor C1 as a clock voltage signal CLK and a high (H) signal (as an inverted clock voltage signal CLK_inv) (VDD) signal is input. The output voltage Vout is a negative voltage.

When the clock voltage signal CLK changes from the positive voltage VDD signal to the low voltage signal L in the second state, the voltage of the first node N1 becomes the negative voltage due to the characteristic of the capacitor to maintain the voltage. The negative voltage signal of the first node N1 is applied to the gate terminals of the third switching transistor M3 and the fourth switching transistor M4. Thus, the third switching transistor M3 is turned on and the fourth switching transistor M4 is turned off. Since the third switching transistor M3 is turned on, the voltage of the second node N2 becomes low (L). The 0V signal of the second node N2 is applied to the gate terminal of the first switching transistor Ml to turn off the first switching transistor Ml. The voltage of the third node N3 becomes low (L) by the bootstrap of the fourth capacitor C4 while the inverted clock voltage CLK_inv is changed from the low (L) signal to the high (H) signal. The low (L) signal of the third node N3 is applied to the gate terminal of the second switching transistor M2 to turn on the second switching transistor M2. Accordingly, the second switching transistor M2 is turned on, and the second capacitor C2 is charged with the negative voltage, so that the output voltage Vout becomes the negative voltage.

As a result, in the second state, the first switching transistor Ml and the fourth switching transistor M4 are turned off, and the second switching transistor M2 and the third switching transistor M3 are turned on to turn off the second capacitor C2. And the negative voltage is output through the output terminal 30. [0050]

An operation state at the time of initial start up of the negative voltage supply device according to the embodiment of the present invention will be described.

The output voltage Vout of the output stage 30 starts at the low level L just before the negative voltage supply device is operated and the voltage Vout of the first node N1, the second node N2 and the third node N3 Is a row (L), and all the switching transistors are turned off. When the high (H) signal is input to the clock input terminal 10 in the initial first state, the first capacitor C1 is charged. When the first state is the second state, the clock voltage CLK changes from a high (H) signal to a low (L) signal. Therefore, the voltage of the first node N1 becomes a negative voltage. When the negative voltage signal is applied to the gate terminals of the third switching transistor M3 and the fourth switching transistor M4, the third switching transistor M3 is turned on and the fourth switching transistor M4 is turned off do. The voltage of the second node N2 becomes low (L) because the third switching transistor M3 is turned on. The voltage of the second node N2 keeps the first switching transistor M1 in the OFF state. The voltage of the third node N3 is low and the source voltage of the second switching transistor M2 becomes a negative voltage so that the second switching transistor M2 is turned on and the second capacitor C2 is charged And the output terminal 30 outputs a negative voltage.

Therefore, in the negative voltage supplying device according to the embodiment of the present invention, the gate driving method of each switching transistor is such that even if the output voltage Vout of the output stage 30 starts the negative charging and pumping operation at a low (L) There is no problem.

As described above, according to an embodiment of the present invention, a negative voltage supply device can be easily implemented. That is, the two clock signals which are opposite to each other as described above are received, and the charging and discharging of the capacitor are repeated according to the clock signal, and the negative voltage can be supplied at the output terminal. In particular, since the third switching transistor M3, the fourth switching transistor M4, the third capacitor C3, and the fourth capacitor C4 for bootstrap can be implemented in a small size, Is possible. Therefore, it is possible to solve problems such as space utilization and cost reduction.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

10: Clock input stage
20: Inverting clock input
101: first switching unit
102:
103: a third switching unit
104: fourth switching unit
110: first charging unit
111: first bootstrap part
112: second bootstrap part
120: second charging unit

Claims (6)

A negative voltage supply device for supplying a negative voltage,
A clock signal is inputted to one end and a first trigger is selectively connected to the ground terminal or the output terminal of the negative voltage supply device according to the clock signal;
A second charging unit having one end connected to the output terminal and the other end grounded;
A first switching unit inserted between the other end of the first charging unit and the ground terminal;
A second switching unit inserted between the other end of the first charging unit and the output terminal; And
A bootstrap part for bootstrapping an inverted clock signal and providing an on / off control signal to the first switching part and the second switching part,
/ RTI >
Negative voltage supply. delete The method according to claim 1,
A third switching unit inserted between the bootstrap unit and the ground terminal; And
And a fourth switching unit inserted between the bootstrap unit and the output terminal,
Wherein the on / off state of the third switching unit and the fourth switching unit is controlled by a voltage signal at the other end of the first charging unit.
Negative voltage supply. The method of claim 3,
The bootstrap unit includes:
A first capacitor inserted between an input terminal of the inverted clock signal and a control signal input terminal of the first switching unit; And
And a second capacitor inserted between an input terminal of the inverted clock signal and a control signal input terminal of the second switching unit.
Negative voltage supply. 5. The method of claim 4,
Wherein the first charge /
And the second clock signal is connected to the ground terminal when the clock signal is a high signal and is connected to the second charging unit when the clock signal is a low signal,
Wherein the second charge /
(L) signal when the clock signal is a high (H) signal, and is connected to a control signal input terminal of the second switching unit when the clock signal is a low
Negative voltage supply. 6. The method according to any one of claims 3 to 5,
At least one of the first switching unit and the third switching unit includes a P-type transistor,
At least one of the second switching unit and the fourth switching unit includes an N-type transistor,
Negative voltage supply.

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