CN113938004B - Voltage doubling inverter, power supply voltage conversion circuit and electronic product - Google Patents
Voltage doubling inverter, power supply voltage conversion circuit and electronic product Download PDFInfo
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- CN113938004B CN113938004B CN202111016637.6A CN202111016637A CN113938004B CN 113938004 B CN113938004 B CN 113938004B CN 202111016637 A CN202111016637 A CN 202111016637A CN 113938004 B CN113938004 B CN 113938004B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a voltage doubling inverter, which comprises: an oscillator module for generating a clock signal; the charge pump module is connected with the oscillator module and is used for processing the periodic square wave signal by utilizing the clock signal to obtain a square wave signal carrying high voltage and negative voltage; and the whole amplitude module is connected with the charge pump module and is used for carrying out whole amplitude on the square wave signal carrying the high voltage and the negative voltage to obtain a stable voltage doubling inversion output signal. The voltage-multiplying inverter provided by the invention greatly reduces the system power consumption, simplifies the circuit structure, reduces the chip area and improves the conversion efficiency.
Description
Technical Field
The invention belongs to the technical field of power supply voltage conversion, and particularly relates to a voltage doubling inverter, a power supply voltage conversion circuit and an electronic product.
Background
With the development of integrated circuit industry, various products are continuously and iteratively updated, and higher performance is proposed for the internal performance of each product, in the field of power management chips (LDO, DC-DC, etc.), power tubes gradually apply NMOS as a main driving tube, but in order to obtain better driving effect, voltage doublers are often required to be used for doubling the power supply voltage so as to obtain larger driving effect, and in addition, a simple and practical high-performance voltage doubler inverter is urgently required in many other fields such as LCD displays, cellular phone power amplifiers, PDAs, portable data recorders, etc. to improve the comprehensive performance of the products.
However, the existing voltage-doubling inverter often realizes corresponding functions through a large number of complex circuit combinations, so that the circuit power consumption is obviously increased, the chip area is larger, and the conversion efficiency is not high.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a voltage doubler inverter. The technical problems to be solved by the invention are realized by the following technical scheme:
the present invention provides a voltage doubler inverter comprising:
an oscillator module for generating a clock signal;
the charge pump module is connected with the oscillator module and is used for processing the periodic square wave signal by utilizing the clock signal to obtain a square wave signal carrying high voltage and negative voltage;
and the whole amplitude module is connected with the charge pump module and is used for carrying out whole amplitude on the square wave signal carrying high voltage and negative voltage to obtain a stable voltage doubling inversion output signal.
In one embodiment of the invention, the oscillator module comprises a miniature charge pump circuit, a comparator, a D-flip-flop, and an inverter; the miniature charge pump circuit is provided with a first input end, a second input end and a third input end, wherein the first input end is connected with a power supply voltage end VDD, and the second input end and the third input end are both connected with the output end of the comparator;
the positive phase input end of the comparator is connected with the output end of the miniature charge pump circuit, the negative phase input end of the comparator is connected with the reference voltage end VREF, and the output end of the comparator is connected with the CP input end of the D trigger;
the output Q end of the D trigger is used as a first output end of the oscillator module to output a clock signal CLK;
the input end of the inverter is connected with the output Q end of the D trigger, and the output end of the inverter is used as the second output end of the oscillator module to output the reverse clock signal CLK_.
In one embodiment of the present invention, the micro charge pump circuit includes a current source, a first PMOS transistor, a first NMOS transistor, and a first capacitor; wherein,
the input end of the current source is used as a first input end of the miniature charge pump circuit and is connected with a power supply voltage end VDD, and the output end of the current source is connected with the source electrode of the first PMOS tube and the substrate;
the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are respectively used as a second input end and a third input end of the miniature charge pump circuit and are connected with the output end of the comparator;
the source electrode of the first NMOS tube is grounded;
the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and is grounded through the first capacitor;
the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube and the common end of the first capacitor are used as the output end of the miniature charge pump circuit and are connected with the non-inverting input end of the comparator.
In one embodiment of the present invention, the charge pump module includes a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a second NMOS transistor, a third NMOS transistor, a second PMOS transistor, and a third PMOS transistor; wherein,
one end of the second capacitor and one end of the fourth capacitor are connected with the first output end of the oscillator module together;
the other end of the second capacitor, the source electrode of the second NMOS tube and the grid electrode of the third NMOS tube are connected with each other, and the common end of the second capacitor is used as a first output end of the charge pump module and is connected with a first input end of the whole module;
the other end of the fourth capacitor, the source electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected with each other, and the common end of the fourth capacitor is used as a second output end of the charge pump module and is connected with a second input end of the whole module;
one end of the third capacitor and one end of the fifth capacitor are connected with the second output end of the oscillator module together;
the other end of the third capacitor, the grid electrode of the second NMOS tube and the source electrode of the third NMOS tube are connected with each other, and the common end of the third capacitor is used as a third output end of the charge pump module and is connected with a third input end of the whole module;
the other end of the fifth capacitor, the grid electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected with each other, and the common end of the fifth capacitor is used as a fourth output end of the charge pump module and is connected with a fourth input end of the whole module;
the drain terminals of the second NMOS tube and the third NMOS tube are connected with a power supply voltage terminal VDD;
and the drains of the second PMOS tube and the third PMOS tube are connected with the ground end GND.
In one embodiment of the invention, the whole module comprises a first diode, a second diode, a third diode, a fourth diode, a sixth capacitor and a seventh capacitor; wherein,
the anode of the first diode, the cathode of the second diode, the anode of the third diode and the cathode of the fourth diode are respectively used as first to fourth input ends of the whole module and are sequentially and correspondingly connected with first to fourth output ends of the charge pump module;
one end of the sixth capacitor, the cathode of the first diode and the cathode of the third diode are connected with each other, and the common end of the sixth capacitor is used as a first output end of the whole module to output a voltage doubling signal VH;
one end of the seventh capacitor, the anode of the second diode and the anode of the fourth diode are connected with each other, and the common end of the seventh capacitor is used as a second output end of the whole module to output an inverted voltage signal VL;
the other ends of the sixth capacitor and the seventh capacitor are grounded to the ground GND.
Another embodiment of the present invention further provides a power supply voltage conversion circuit, including the voltage doubler inverter described in the foregoing embodiment.
Another embodiment of the present invention further provides an electronic product, including the power supply voltage conversion circuit described in the foregoing embodiment.
The invention has the beneficial effects that:
the voltage doubling inverter provided by the invention can realize the inversion and voltage doubling functions by adopting the simplest structure, and can work respectively, especially the inversion part can realize inversion without other power inputs when a clock signal is given, thereby greatly reducing the system power consumption, simplifying the circuit structure, reducing the chip area and improving the conversion efficiency.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a voltage doubler inverter according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of an oscillator module according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a charge pump module and an overall module according to an embodiment of the present invention;
fig. 4 is a waveform diagram of voltage doubler and reverse voltage simulation of final output of the voltage doubler inverter according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of a voltage doubler inverter according to an embodiment of the present invention; it comprises the following steps:
an oscillator module 1 for generating a clock signal;
the charge pump module 2 is connected with the oscillator module 1 and is used for processing the periodic square wave signal by utilizing the clock signal to obtain a square wave signal carrying high voltage and negative voltage;
and the whole amplitude module 3 is connected with the charge pump module 2 and is used for carrying out whole amplitude on the square wave signal carrying high voltage and negative voltage to obtain a stable voltage doubling inversion output signal.
Further, referring to fig. 2, fig. 2 is a circuit diagram of an oscillator module according to an embodiment of the present invention, where the oscillator module 1 includes a micro charge pump circuit 11, a comparator 12, a D flip-flop 13, and an inverter 14; wherein,
the miniature charge pump circuit 11 has a first input end, a second input end and a third input end, wherein the first input end is connected with a power supply voltage end VDD, and the second input end and the third input end are both connected with the output end of the comparator 12; the positive phase input end of the comparator 12 is connected with the output end of the miniature charge pump circuit 11, the negative phase input end is connected with the reference voltage end VREF, and the output end of the comparator 12 is connected with the CP input end of the D trigger 13;
the D input end of the D trigger 13 is connected with the output Q_end, and the output Q end of the D trigger 13 is used as a first output end of the oscillator module 1 to output a clock signal CLK;
an input terminal of the inverter 14 is connected to an output Q terminal of the D flip-flop 13, and an output terminal of the inverter 14 outputs a reverse clock signal clk_ as a second output terminal of the oscillator module 1.
Further, the micro charge pump circuit 11 includes a current source I1, a first PMOS transistor P1, a first NMOS transistor N1, and a first capacitor C1; wherein,
the input end of the current source I1 is used as a first input end of the miniature charge pump circuit 11 to be connected with a power supply voltage end VDD, and the output end of the current source I1 is connected with the source electrode of the first PMOS tube P1 and the substrate;
the grid electrode of the first PMOS transistor P1 and the grid electrode of the first NMOS transistor N1 are respectively used as a second input end and a third input end of the micro charge pump circuit 11 and are connected with the output end of the comparator 12;
the source electrode of the first NMOS tube N1 is grounded;
the drain electrode of the first PMOS tube P1 is connected with the drain electrode of the first NMOS tube N1 and is grounded through the first capacitor C1;
the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, and the common terminal of the first capacitor C1 are used as the output terminal of the micro charge pump circuit 11 and connected to the non-inverting input terminal of the comparator 12.
When the oscillator module 1 works, initially, the positive phase end of the comparator CMP is low because no charge is accumulated, the output end a is low, the first PMOS transistor P1 is turned on, the current source I1 charges the first capacitor C1, when the potential of the positive phase end is higher than the reference voltage VREF of the negative phase end, the output end a of the comparator is inverted, the first PMOS transistor P1 is turned off, the first NMOS transistor N1 is turned on to discharge the first capacitor C1, the positive phase end of the comparator CMP is lower than the reference voltage VREF again, the output end is inverted, the a becomes low, the first PMOS transistor P1 is turned on again, the first NMOS transistor N1 is turned off, the current source I1 charges the first capacitor C1 until the potential of the positive phase end is higher than the reference voltage VREF so that the output end a is inverted again, and the comparator output end a generates a narrow pulse signal with a fixed frequency in a cyclic reciprocating manner.
The D flip-flop 13 is converted into a clock signal of 50% duty cycle of two frequency divisions after passing through a frequency divider for the narrow pulse signal from the comparator output a.
Further, referring to fig. 3, fig. 3 is a circuit example diagram of a charge pump module and an entire module according to an embodiment of the present invention; the charge pump module 2 includes a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a second NMOS transistor N2, a third NMOS transistor N3, a second PMOS transistor P2, and a third PMOS transistor P3; wherein,
one end of the second capacitor C2 and one end of the fourth capacitor C4 are connected with the first output end of the oscillator module 1 together;
the other end of the second capacitor C2, the source electrode of the second NMOS transistor N2 and the gate electrode of the third NMOS transistor N3 are connected with each other, and the common end of the second capacitor C2 is used as the first output end of the charge pump module 2 and is connected with the first input end of the whole module 3;
the other end of the fourth capacitor C4, the source electrode of the second PMOS transistor P2 and the gate electrode of the third PMOS transistor P3 are connected with each other, and the common end of the fourth capacitor C4 is used as the second output end of the charge pump module 2 and is connected with the second input end of the whole module 3;
one end of the third capacitor C3 and one end of the fifth capacitor C5 are connected to the second output end of the oscillator module 1 together;
the other end of the third capacitor C3, the gate of the second NMOS transistor N2, and the source of the third NMOS transistor N3 are connected to each other, and the common end of the third capacitor C3 is used as a third output end of the charge pump module 2 and connected to a third input end of the whole module 3;
the other end of the fifth capacitor C5, the gate of the second PMOS transistor P2 and the source of the third PMOS transistor P3 are connected with each other, and the common end of the fifth capacitor C5 is used as the fourth output end of the charge pump module 2 and is connected with the fourth input end of the whole module 3;
the drain terminals of the second NMOS tube N2 and the third NMOS tube N3 are connected with a power supply voltage end VDD;
the drains of the second PMOS transistor P2 and the third PMOS transistor P3 are connected to the ground GND.
Specifically, when CLK is high, the gate of the third NMOS transistor N3 is at a voltage-multiplying high potential, the gate of the second NMOS transistor N2 is at a voltage-multiplying low potential, and the third NMOS transistor N3 is turned on; when CLK_is high potential, the grid electrode of the third NMOS tube N3 is low voltage potential, the grid electrode of the second NMOS tube N2 is high voltage potential, and the second NMOS tube N2 is conducted;
when CLK_is high potential, the third PMOS tube P3 is conducted, and the source electrode of the third PMOS tube P3 and the grid electrode of the second PMOS tube P2 are reduced to ground potential; when CLK is at high potential, the third PMOS transistor P3 is turned off because energy in the capacitor cannot be suddenly changed, the gate of the second PMOS transistor P2 becomes negative potential, and the gate of the third PMOS transistor P3 is at ground potential.
In this embodiment, the charge pump module 2 charges and discharges the capacitor by the voltage doubling inversion main module depending on the on and off of the MOS transistor, and simultaneously obtains a square wave signal carrying high voltage and negative voltage.
Further, please continue to refer to fig. 3, wherein the whole module 3 includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a sixth capacitor C6, and a seventh capacitor C7; wherein,
the positive electrode of the first diode D1, the negative electrode of the second diode D2, the positive electrode of the third diode D3 and the negative electrode of the fourth diode D4 are respectively used as the first to fourth input ends of the whole module 3, and are sequentially and correspondingly connected with the first to fourth output ends of the charge pump module 2;
one end of the sixth capacitor C6, the cathode of the first diode D1, and the cathode of the third diode D3 are connected with each other, and the common end thereof is used as the first output end of the whole module 3 to output the voltage doubling signal VH;
one end of the seventh capacitor C7, the positive electrode of the second diode D2, and the positive electrode of the fourth diode D4 are connected to each other, and the common end thereof is used as the second output end of the whole module 3 to output the reverse voltage signal VL;
the other ends of the sixth capacitor C6 and the seventh capacitor C7 are grounded to the ground GND.
In this embodiment, the whole module 3 performs the whole of the square wave signal output by the charge pump module 2 to obtain the voltage doubling output VH of the negative electrodes of the first diode D1 and the third diode D3, and the inverting voltage output VL of the positive electrodes of the second diode D2 and the fourth diode D4.
It should be noted that, in the whole module 3, a MOS transistor may be used as a switch instead of a diode switch to achieve the same function, and the threshold voltage loss may be reduced to the maximum extent, and the detailed implementation process belongs to the prior art in the field, which is not specifically described herein.
The voltage doubling inverter provided by the embodiment can realize the inversion and voltage doubling functions by adopting the simplest structure, and can work respectively, especially the inversion part can realize inversion without other power input when a clock signal is given, so that the system power consumption is greatly reduced, the circuit structure is simplified, the chip area is reduced, and the conversion efficiency is improved.
Another embodiment of the present invention provides a power supply voltage conversion circuit, including the voltage doubler inverter provided in the above embodiment. Therefore, the power supply voltage conversion circuit also has the advantages of reducing the system power consumption, simplifying the circuit structure, reducing the chip area and improving the conversion efficiency.
Still another embodiment of the present invention provides an electronic product, including the power supply voltage conversion circuit provided in the above embodiment.
Example two
The following describes the advantageous effects of the voltage doubler inverter according to the first embodiment through a simulation test.
The simulation result obtained by the Cadence simulation platform is shown in fig. 4, and fig. 4 is a simulation waveform diagram of the voltage doubling and inversion voltage finally output by the voltage doubling inverter provided by the embodiment of the invention. When the input voltage is 10V, the voltage doubling output voltage is 19.44V, and the inverted output voltage is-9.3V. It is difficult to achieve accurate 20V voltage-doubler output and-10V inverted voltage output because the diode consumes a portion of the turn-on voltage. From the above results, the voltage doubling inverter with simple structure provided by the invention can realize the functions of inversion and voltage doubling.
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (6)
1. A voltage doubler inverter, comprising:
an oscillator module (1) for generating a clock signal;
the charge pump module (2) is connected with the oscillator module (1) and is used for obtaining a square wave signal carrying high voltage and negative voltage by utilizing the clock signal;
the whole amplitude module (3) is connected with the charge pump module (2) and is used for carrying out whole amplitude on the square wave signals carrying high voltage and negative voltage to obtain stable voltage doubling inversion output signals;
the charge pump module (2) comprises a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a fifth capacitor (C5), a second NMOS tube (N2), a third NMOS tube (N3), a second PMOS tube (P2) and a third PMOS tube (P3); wherein one end of the second capacitor (C2) and one end of the fourth capacitor (C4) are commonly connected with a first output end of the oscillator module (1);
the other end of the second capacitor (C2), the source electrode of the second NMOS tube (N2) and the grid electrode of the third NMOS tube (N3) are connected with each other, and the common end of the second capacitor is used as a first output end of the charge pump module (2) and is connected with a first input end of the whole module (3);
the other end of the fourth capacitor (C4), the source electrode of the second PMOS tube (P2) and the grid electrode of the third PMOS tube (P3) are connected with each other, and the common end of the fourth capacitor is used as a second output end of the charge pump module (2) and is connected with a second input end of the whole module (3);
one end of the third capacitor (C3) and one end of the fifth capacitor (C5) are commonly connected with a second output end of the oscillator module (1);
the other end of the third capacitor (C3), the grid electrode of the second NMOS tube (N2) and the source electrode of the third NMOS tube (N3) are connected with each other, and the common end of the third capacitor is used as a third output end of the charge pump module (2) and is connected with a third input end of the whole module (3);
the other end of the fifth capacitor (C5), the grid electrode of the second PMOS tube (P2) and the source electrode of the third PMOS tube (P3) are connected with each other, and the common end of the fifth capacitor is used as a fourth output end of the charge pump module (2) and is connected with a fourth input end of the whole module (3);
the drain terminals of the second NMOS tube (N2) and the third NMOS tube (N3) are connected with a power supply voltage end VDD;
the drains of the second PMOS tube (P2) and the third PMOS tube (P3) are connected with the ground end GND.
2. The voltage doubler inverter according to claim 1, characterized in that the oscillator module (1) comprises a miniature charge pump circuit (11), a comparator (12), a D-flip-flop (13) and an inverter (14); wherein,
the miniature charge pump circuit (11) is provided with a first input end, a second input end and a third input end, wherein the first input end is connected with a power supply voltage end VDD, and the second input end and the third input end are both connected with the output end of the comparator (12);
the positive phase input end of the comparator (12) is connected with the output end of the miniature charge pump circuit (11), the negative phase input end is connected with the reference voltage end VREF, and the output end of the comparator (12) is connected with the CP input end of the D trigger (13);
the D input end of the D trigger (13) is connected with the output Q_end, and the output Q end of the D trigger (13) is used as a first output end of the oscillator module (1) to output a clock signal CLK;
the input end of the inverter (14) is connected with the output Q end of the D trigger (13), and the output end of the inverter (14) is used as the second output end of the oscillator module (1) to output an inverse clock signal CLK_.
3. The voltage doubler inverter according to claim 2, wherein the micro charge pump circuit (11) comprises a current source (I1), a first PMOS transistor (P1), a first NMOS transistor (N1), and a first capacitor (C1); the input end of the current source (I1) is used as a first input end of the miniature charge pump circuit (11) to be connected with a power supply voltage end VDD, and the output end of the current source is connected with the source electrode and the substrate of the first PMOS tube (P1);
the grid electrode of the first PMOS tube (P1) and the grid electrode of the first NMOS tube (N1) are respectively used as a second input end and a third input end of the miniature charge pump circuit (11) and are connected with the output end of the comparator (12);
the source electrode of the first NMOS tube (N1) is grounded;
the drain electrode of the first PMOS tube (P1) is connected with the drain electrode of the first NMOS tube (N1), and is grounded through the first capacitor (C1);
the drain electrode of the first PMOS tube (P1), the drain electrode of the first NMOS tube (N1) and the common end of the first capacitor (C1) are used as the output end of the miniature charge pump circuit (11) and connected with the non-inverting input end of the comparator (12).
4. The voltage doubler inverter according to claim 1, characterized in that the whole block (3) comprises a first diode (D1), a second diode (D2), a third diode (D3), a fourth diode (D4), a sixth capacitance (C6) and a seventh capacitance (C7); wherein,
the positive electrode of the first diode (D1), the negative electrode of the second diode (D2), the positive electrode of the third diode (D3) and the negative electrode of the fourth diode (D4) are respectively used as first to fourth input ends of the whole module (3) and are sequentially and correspondingly connected with first to fourth output ends of the charge pump module (2);
one end of the sixth capacitor (C6), the cathode of the first diode (D1) and the cathode of the third diode (D3) are connected with each other, and the common end of the sixth capacitor is used as a first output end of the whole module (3) to output a voltage doubling signal VH;
one end of the seventh capacitor (C7), the positive electrode of the second diode (D2) and the positive electrode of the fourth diode (D4) are connected with each other, and the common end of the seventh capacitor is used as a second output end of the whole module (3) to output an inversion voltage signal VL;
the other ends of the sixth capacitor (C6) and the seventh capacitor (C7) are grounded to the ground GND.
5. A power supply voltage conversion circuit comprising the voltage doubler inverter according to any one of claims 1 to 4.
6. An electronic product comprising the power supply voltage conversion circuit according to claim 5.
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