KR100293628B1 - Circuit for decreasing a standby current in a semiconductor memory device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a standby current reduction circuit of a semiconductor memory device.

2. Technical problem to be solved by the invention

In the standby mode of the semiconductor memory device, a high standby current is consumed in proportion to the supply voltage, making it difficult to use in a field requiring battery backup and low power consumption, and also causing difficulty in ensuring data retention.

3. Summary of the Solution of the Invention

In the present invention, the normal operation is performed when the chip is enabled according to the / CS signal, and when the chip is disabled, the VDC is driven according to the disable cycle, thereby using data lower than the power supply voltage supplied to the VDC. The standby current is reduced by reducing it to the minimum voltage that can be maintained.

Description

Circuit for decreasing a standby current in a semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standby current reduction circuit of a semiconductor memory device, and in particular, a chip select signal of a static random access memory (SRAM) is continuously disabled for a certain cycle. ), And a standby current reduction circuit of a semiconductor memory device capable of reducing a standby current by operating a voltage down circuit (VDC) according to the detected signal.

In a semiconductor device, a power supply voltage is reduced to a constant level in a voltage drop circuit (VDC) according to a chip select bar (/ CS) signal, and the reduced voltage is supplied to the cell area to be used as the power supply voltage of the cell area. do.

SRAM devices are difficult to use in applications requiring battery back up and low power consumption by consuming high standby current in proportion to the supply voltage in standby mode. Difficulties arise in ensuring the characteristics of the back.

The standby current ISB is obtained as shown in Equation 1 below.

Where V _CC is the power supply voltage, R _load is the load resistance, I _off is the TFT off current, and α is the off current of the peripheral circuit transistor.

That is, as shown in Equation 1, the standby current increases in proportion to the number of cells, the power supply voltage, the TFT off current, and the off current of the peripheral circuit transistor, and decreases in proportion to the load resistance.

Accordingly, an object of the present invention is to provide a standby current reduction circuit of a semiconductor memory device capable of reducing a standby current.

The present invention for achieving the above object is a logic means that one input terminal is maintained in the ground state and the chip select bar signal is input to the other input terminal, and the chip is disabled according to the chip enable bar signal A disable cycle control means for controlling the output signal of said logic means during a disable cycle, and an inverter for inverting the output signal of said disable cycle control means, according to a signal inverted through said inverter. From the power supply voltage or a reference voltage lower than the power supply voltage can be selectively output.

1 is a circuit diagram of a standby current reduction circuit of a semiconductor memory device according to the present invention.

2 is a circuit diagram of a disable cycle control circuit according to another embodiment of the present invention.

3 is a detailed circuit diagram of the voltage drop circuit of FIG.

<Description of the symbols for the main parts of the drawings>

10: voltage drop circuit

20: disable cycle control circuit

11: NOR gate

P1 to P3: first to third PMOS transistors of standby current reduction circuit

N1 to N3: first to third NMOS transistors of standby current reduction circuit

M1 to M3: first to third transfer widgets of the standby current reduction circuit

I1 to I10: first to tenth inverters of the standby current reduction circuit

K1 to K4: first to fourth nodes of the standby current reduction circuit

P11: PMOS transistor in disable cycle control circuit

N11: NMOS transistor in disable cycle control circuit

I11 and I12: first and second inverters of the disable cycle control circuit

K11: first node of the disable cycle control circuit

C: Capacitor of Disable Cycle Control Circuit

P21 to P24: first to fourth PMOS transistors of the voltage drop circuit

N21 to N24: first to fourth NMOS transistors in voltage drop circuit

K21 to K23: first to third nodes of the voltage drop circuit

The present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a standby current reduction circuit of a semiconductor memory device according to the present invention, including a NOR 11 for outputting a logic signal according to a chip select bar (/ CS) signal and a ground signal, and an output of the NOR gate 11. A disable cycle control circuit 20 driven according to the signal and an inverter I10 for inverting the output signal of the disable cycle control circuit, wherein the output signal of the inverter I10 is a voltage drop circuit. It is used as a control signal in (10).

First, the circuit driving when the / CS signal in the low state is applied and enabled is as follows.

The / CS signal of the low state is inputted to the other input terminal of the NOR gate 11 in which one input terminal maintains the ground state, and the high state signal is outputted so that the first node K1 maintains the potential of the high state. do.

The first PMOS transistor P1 is turned off by the signal in the high state. In addition, since the high state signal is inverted to the low state through the first inverter I1 and the high state signal is inverted to the high state through the second inverter I2, the first transfer gate M1 is turned off. The first NMOS transistor N1 is turned on by the signal inverted to the high state through the second inverter I2 and the potential is passed to the ground so that the second node K2 is turned low, and the third inverter I3 is turned on. Is reversed to the high state.

The second PMOS transistor P2 is turned off by the signal inverted to the high state through the third inverter I3. In addition, since the signal inverted to the high state through the second inverter I2 is inverted to the low state through the fourth inverter I4 and inverted to the high state through the fifth inverter I5, the second transfer gate M2. ) Is turned off. By the signal inverted to the high state through the fifth inverter I5, the second NMOS transistor N2 is turned on to pass the potential to the ground so that the third node K3 is turned low, and the sixth inverter I6 Is reversed to the high state.

The third PMOS transistor P3 is turned off by the signal inverted to the high state through the sixth inverter I6. In addition, since the signal inverted to the high state through the fifth inverter I5 is inverted to the low state through the seventh inverter I7 and inverted to the high state through the eighth inverter I8, the third transfer gate M3. ) Is turned off. The third NMOS transistor N3 is turned on by the signal inverted to the high state through the eighth inverter I8 to pass the potential to the ground so that the fourth node K4 is turned low, and the ninth inverter I9 Is reversed to the high state.

The signal output through the multi-stage disable cycle control circuit is inverted to a low state through the tenth inverter I10 and input as a control signal of the voltage drop circuit 10.

The circuit driving when the / CS signal in the high state is applied and disabled is as follows.

The / CS signal of the high state is inputted to the other input terminal of the NOR gate 11 in which one input terminal maintains the ground state, and the low state signal is outputted, so that the potential of the low state is maintained in the first node K1. do.

The first PMOS transistor P1 is turned on by the low signal to apply the power supply voltage V _CC . In addition, since the signal in the low state is inverted to the high state through the first inverter I1 and inverted to the low state through the second inverter I2, the first transfer gate M1 is turned on to transmit the signal in the high state. The potential of the second node K2 becomes high. The first NMOS transistor N1 is turned off by the signal inverted to the low state through the second inverter I2, so that the second node K2 is kept high and the low state through the third inverter I3. Is reversed.

The second PMOS transistor P2 is turned on by the signal inverted to the low state through the third inverter I3 to apply the power supply voltage V _CC . In addition, since the signal inverted to the low state through the second inverter I2 is inverted to the high state through the fourth inverter I4 and inverted to the low state through the fifth inverter I5, the second transfer gate M2. ) Is turned on to transmit a high state signal so that the potential of the third node K3 becomes high. Since the second NMOS transistor N2 is turned off by the signal inverted to the low state through the fifth inverter I5, the potential of the third node K3 is maintained in the high state, and through the sixth inverter I6. Inverted to the low state.

The third PMOS transistor P3 is turned on by the signal inverted to the low state through the sixth inverter I6 to apply the power supply voltage V _CC . In addition, since the signal inverted to the low state through the fifth inverter I5 is inverted to the high state through the seventh inverter I7 and inverted to the low state through the eighth inverter I8, the third transfer gate M3. ) Is turned on to transmit a signal in a high state, and the fourth node K4 becomes high. The third NMOS transistor N3 is turned off by the signal inverted to the low state through the eighth inverter I8 so that the fourth node K4 is kept high and the low state through the ninth inverter I9. The signal inverted to is input to the voltage drop circuit 10.

The signal output through the multi-stage disable cycle control circuit is inverted to a high state through the tenth inverter I10 and input as a control signal of the voltage drop circuit 10.

That is, a high state signal is output when a low / CS signal is applied and enabled, and a low state signal is output when a high / CS signal is applied and disabled.

As described above, the disable cycle control circuit 20 may be configured in multiple stages according to the size and disable cycle of the transistor constituting the disable cycle control circuit 20. That is, one cycle may be controlled or more cycles may be controlled according to the size of the transistor determined according to the width and the length. 1 illustrates an example of a cycle of a disable signal and a size of a transistor capable of controlling the cycle. For example, if the transistor size of the disable cycle control circuit can control one cycle, and if the disable cycle is one cycle, the disable cycle control circuit is configured as one end, and the transistor size of the disable cycle control circuit is 1 cycle. The cycle can be controlled and the disable cycle control circuit is configured in three stages when the disable cycle is three cycles.

2 is a circuit diagram of another embodiment of a disable cycle control circuit of the standby current reduction circuit according to the present invention.

First, the circuit driving when the / CS signal in the low state is applied and enabled is as follows.

Similar to the standby current reduction circuit of FIG. 1, a / CS signal in a low state is input to another input terminal of a NOR gate (not shown) in which one input terminal maintains a ground state, and a high state signal is output. The PMOS transistor P11 is turned off by the signal in the high state. In addition, the signal in which the high state signal is inverted to the low state through the first inverter I11 and the high state signal turn off the transfer gate M11. That is, the signal inverted to the low state through the first inverter I11 is input to the NMOS transistor side of the transfer gate M11, and the high state signal is input to the PMOS transistor side to turn off the transfer gate M11. Since the NMOS transistor N11 is turned on by the signal in the high state to form a path to the ground, the first node K11 becomes low. Since the first node K11 maintains a low state, the first node K11 is inverted to a high state through the second inverter I12 without affecting the capacitor C. This circuit is constructed in multiple stages according to the disable cycle as described in FIG.

The circuit driving when the / CS signal in the high state is applied and disabled is as follows.

Similar to the standby current reduction circuit of FIG. 1, the / CS signal of the high state is input to the other input terminal of the NOR gate (not shown) in which one input terminal maintains the ground state, and the low state signal is output. The PMOS transistor P11 that controls the signal for disabling by the low signal for one cycle is turned on to apply the power supply voltage V _CC . In addition, the signal in which the low state signal is inverted to the high state through the first inverter I11 and the low state signal turn on the transfer gate M11 to transmit the applied power voltage. That is, the signal inverted to the high state through the first inverter I11 is input to the NMOS transistor side of the transfer gate M11, and the signal of the low state is input to the PMOS transistor side to turn on the transfer gate M11. The NMOS transistor N11 is turned off by the low state signal, the high state signal is transmitted through the transfer gate M11, and the first node K11 is made high. However, since the high state signal is transmitted, it charges the capacitor C and controls the signal that is disabled during the second cycle. The signal in the high state is inverted to the low state through the second inverter I12. This circuit is constructed in multiple stages according to the disable cycle as in FIG.

According to another exemplary embodiment of the present invention, the size of the PMOS transistor P11 and the capacitor C and multiple stages of the PMOS transistor P11 and the capacitor C may be used to adjust the / CS disable cycle.

3 is a detailed circuit diagram of the voltage drop circuit 10 of FIG. 1 and is operated by inputting an output signal of a standby current reduction circuit and a reference voltage V _ref .

When the / CS signal in the low state is applied and enabled, the third and fourth NMOS transistors N23 and N24 are turned off using the low state signal output through the standby current reduction circuit as an input, and the fourth PMOS transistor is turned on. (P24) is turned on. Accordingly, the first and second PMOS transistors P21 and P22, the first and second NMOS transistors N21 and N22, and the first and second PMOS transistors that are driven by applying a reference voltage of about 2.0V, for example, a data holding voltage of the SRAM. The 3 PMOS transistor P23 is not driven, and the power supply voltage V _CC applied by the turned on fourth PMOS transistor P24 is output to the output terminal. This output signal is supplied to the cell region and used as the driving voltage of the cell.

When the / CS signal in the high state is applied and disabled, the third and fourth NMOS transistors N23 and N24 are turned on to form a path to ground by using the high state signal outputted through the standby current reduction circuit as an input. The fourth PMOS transistor P24 is turned off.

A reference voltage of, for example, 2.0V from the reference voltage generator circuit is applied to the gate of the first NMOS transistor N21 to weakly turn on the first NMOS transistor N21. The power supply voltage V _CC is applied through the first PMOS transistor P21 acting as a diode, but is passed to ground through the first and third NMOS transistors N21 and N23 which are turned on, so that the first node K21 has a first voltage. The low state where the 3 PMOS transistor P23 is not turned off is maintained. The third PMOS transistor P23 is weakly turned on by the potential of the first node K21 that maintains the low state, and the second node K22 is 2.0V by voltage distribution with the turned on fourth NMOS transistor N24. The reference voltage level is maintained. The potential of this second node K22 is used as the driving voltage of the cell region. In addition, since the second NMOS transistor N22 is weakly turned on by the potential of the second node K22 and the third node K23 is turned low, the second PMOS transistor P22 is turned on.

As described above, when the chip is disabled, the disable cycle control circuit 20 detects this and drives the voltage drop circuit 10 during the disable cycle to output a reference voltage lower than the power supply voltage. It does not affect the dropping circuit 10 so that a power supply voltage is output. This reduces the standby current by supplying the cell array with a reference voltage lower than the supply voltage while the chip is disabled.

Table 1 shows the standby current generated when the standby current reduction circuit is not used in the conventional method and the standby current generated when the standby current reduction circuit is used in the 4M SRAM driven at 3.0V and 5.0V.

4M SRAM Drive Voltage Conventional method Method of the invention 5.0 V 100㎂ 15㎂ 3.0 V 50㎂ 15㎂

As described above, according to the present invention, since the power supply voltage supplied from the outside is reduced to the reference voltage by the voltage drop circuit and supplied to the cell area when the chip is disabled, a voltage lower than that of the conventional power supply voltage is applied. This significantly reduces the standby current.

Claims (4)

Logic means in which one input terminal remains grounded and a chip select bar signal is input to the other input terminal, Disable cycle control means for controlling the output signal of the logic means during a disable cycle when the chip is disabled according to the chip enable bar signal and outputting a signal having a potential opposite to the signal when disabled; And an inverter for inverting an output signal of the disable cycle control means to selectively output a power supply voltage and a reference voltage lower than the power supply voltage from the voltage drop circuit according to the signal inverted through the inverter. Standby current reduction circuit of a semiconductor memory device. 2. The standby current reduction circuit of a semiconductor memory device according to claim 1, wherein said disable cycle control means is configured in multiple stages in accordance with a disable cycle. 2. The apparatus of claim 1, wherein the disable cycle control means comprises: first switching means for applying a power supply voltage according to an output signal of the logic means; A transmission gate for transmitting a power supply voltage input through said first switching means in accordance with an output signal of said logic means; Second switching means for converting a level of a signal transmitted through the transmission gate in accordance with an output signal of the logic means; And an inverter for inverting a signal whose level is converted by the second switching means. 2. The apparatus of claim 1, wherein the disable cycle control means comprises: first switching means for applying a power supply voltage according to an output signal of the logic means; A transmission gate for transmitting a power supply voltage input through said first switching means in accordance with an output signal of said logic means; A capacitor delaying a signal transmitted through the transmission gate; Second switching means for converting a level of a signal transmitted through the transmission gate in accordance with an output signal of the logic means; And an inverter for inverting a signal whose level is converted by the second switching means.