JPH0395796A - Voltage generating circuit - Google Patents

Abstract

PURPOSE:To reduce current consumption at standby by preventing a first voltage setting means from being operated when a memory cell array is not operated, namely, at the standby, and supplying a bias voltage to the memory cell array based on a divided voltage from a second voltage setting means. CONSTITUTION:A first voltage set part 1 to make the current flowing and to set a prescribed voltage V1 only when a chip enable signal CE is set to a low level 'L', namely, when a memory cell array 52 is operated, and a second voltage set part 2 is provided to divide a power supply voltage Vcc and to set a prescribed voltage V2 while being interlocked with the voltage set part 1 only when the chip enable signal CE is set to a high level 'H', namely, when the memory cell array 52 is not operated, a voltage supply part 3 to set the voltages V1 and V2 from the first and second voltage set parts 1 and 2 to prescribed voltages VPC1 and VPC2 and to supply these voltages to be memory cell array 52 as the bias voltage are provided. Thus, the current does not flow at the standby time and the optimum bias voltage can be always generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage generation circuit that generates a constant voltage applied as a bias voltage to a memory cell array.

[Conventional technology]

In order to stabilize and speed up reading from a memory cell array of a MOS memory, it is generally necessary to apply a constant bias voltage to the memory cell array.

Conventionally, a voltage generating circuit as shown in FIG. 2 has been used to generate this constant voltage. The voltage generating circuit shown in FIG. 2 generates a predetermined voltage V. a voltage setting section 50 that gives
The voltage ■ from the voltage setting section 50 is the voltage V. The memory cell array 52 is provided with a voltage supply section 51 which supplies this as a bias voltage to the memory cell array 52. Voltage V,. are applied to the memory cell array 52 via the transistor arrays TR1 to TR, and the transistor arrays TR1 to TRn directly apply the voltage "PC" to the memory cell array 52 when the signal PC is at a high level "H". It is controlled so that the voltage is applied to the bit line of .
The capacitance Cs consists of the source and substrate capacitance of the transistor arrays TR1 to TRn, and has a size proportional to the size of the memory cell array. Voltage setting section 5
0 is composed of n-channel enhancement type MOS transistors Q21, Q22, Q24 and an n-channel depletion type MOS transistor Q23, and the voltage supply section 51 is composed of an n-channel enhancement type MOS transistor Q25.

In the voltage generating circuit having such a configuration, the MOS transistors Q. 2122 to Q, so the voltage V at terminal N21. is set first.

This voltage V. ' is small enough to drive the memory cell array 52, but this voltage Vo is applied to the gate of the MOS transistor Q24 of the voltage setting section 50, and the voltage Vo is applied to the gate of the MOS transistor Q24 of the inverter configuration.
Q24 causes voltage V to be applied to terminal N22. is output as That is, the MOS transistor Q23 has a function as a load section of the inverter, and the voltage V is the power supply voltage V. 0 and 0 MOS transistor Q threshold voltage V and 23
THLO is set to a predetermined size (V-V) and CC T
HLO Ru. Note that the voltage V. In order to maintain this, a current always flows from MOS transistor Q21 to MOS transistor Q22 to always apply voltage V to the gate of MOS transistor Q24, and a current always flows from MOS transistor Q23 to MOS transistor Q24. need to be.

Voltage V from voltage setting section 50. is applied to the voltage supply unit 51, that is, the gate of the MOS transistor Q25, and thereby the voltage 2, from the drain of the MOS transistor Q25, that is, the terminal N23. The output is closed. That is, if the threshold voltage of MOS transistor Q25 is VTE, the voltage is V. is VPC=Vo-VT[
. . . Output as (1).

This voltage VP to the bit lines of memory cell array 52
The application of c is performed prior to sensing the memory cell array 52, thereby making it possible to improve the access time to the memory cell array 52.

[Problem to be solved by the invention]

By the way, in the conventional voltage generating circuit described above, the voltage V
, Vpc at a predetermined value, each MOS transistor Q . Q, 2
122 It is necessary to keep current flowing through Q and Q at all times.

2324 Such a voltage generation circuit has no problem when applied to a good memory cell array such as an NMOS memory where standby current is not considered, but it is required that almost no standby current flows as in a CMOS memory. When applied to a memory cell array, it is necessary to change the configuration so that no current flows during standby. For example, during standby, the voltage ■ is the power supply voltage V. 0 or the ground potential 0 ■. However, during standby, the voltage is fixed at V or V.
In the case of CC GND, the voltage ■ takes the value of (■CC-■TE" or PC or vGND, and the predetermined voltage value (VCC-VTIILOVTE) to be applied to the memory cell array 52.
), and the access time when returning from the standby state to the active state is
,. The disadvantage was that it was slow depending on the return of .

SUMMARY OF THE INVENTION An object of the present invention is to provide a voltage generating circuit that does not allow current to flow during standby and can always generate an optimal bias voltage.

[Means to solve the problem]

To achieve the above object, the present invention provides a first voltage setting means that does not operate when the memory cell array is not in operation and outputs a predetermined voltage when the memory cell array is in operation; a second voltage setting means for outputting a voltage of The memory cell array is characterized by comprising voltage supply means for supplying a predetermined bias voltage to the memory cell array.

[Effect]

In the above-mentioned voltage generating circuit, when the memory cell array is not in operation, a predetermined voltage divided by the second voltage setting means is applied to the voltage supply means, and is supplied to the memory cell array as a predetermined bias voltage. Ru. At this time,
The first voltage setting means does not operate and no current flows as a whole. During operation of the memory cell array, a current flows through the first voltage setting means, and a predetermined voltage is applied from the first voltage setting means to the voltage supply means, and is supplied to the memory cell array as a predetermined bias voltage. [Example] Hereinafter, an example of the present invention will be described based on the drawings.

FIG. 1 is a configuration diagram of an embodiment of a voltage generating circuit according to the present invention. Note that in FIG. 1, the same parts as in FIG. 2 are given the same reference numerals.

Referring to FIG. 1, in the voltage generating circuit of this embodiment, a current flows only when the chip enable signal CE is at a low level "L", that is, when the memory cell array 52 is operating. The setting section 1 works in conjunction with the first voltage setting section 1 to divide the power supply voltage V to set a predetermined voltage V2 when the chip enable signal CB is at a high level "H", that is, when the memory cell array 52 is not operating. The voltages V,■ from the second voltage setting section 2, the lth voltage setting section 1, and the second voltage setting section 2 are set to a predetermined voltage v,■ of 12, and this is set as the bias voltage PCI.
The memory cell array 52 is provided with a voltage supply unit 3 serving as a PC2.

The first voltage setting unit 1 includes n-channel enhancement type MOS transistors Q11, Q12'' 14, Q17, and a p-channel enhancement type MOS transistor Q.
．． It is composed of 1316 MOS transistors Q11, Q1-2, Q13, Q14.
is the MOS} transistor Q21"22 shown in FIG.
'Q, Q and their R capabilities are 2324 corresponding to each other.

The second voltage setting section 2 is constituted by a capacitor C1?2, and when the first voltage setting section 1 is not operating and no current is flowing through the first voltage setting section 1, the second voltage setting section 2 is configured with a capacitor C1? The voltage vcc is divided by capacitors C1 and C to output a voltage v2. Further, the voltage supply unit 3 is an n-channel enhancement type M
It is composed of OS transistors.

Next, the operation of the voltage generating circuit having such a configuration will be explained.

First, when the chip enable signal CB is at a high level "H", that is, when the memory cell array 52 is not operating,
In the first voltage setting section 1, the MOS transistor Q13 is off and the MOS transistor Q is on, so that the voltage at the terminal N12 is close to zero potential, and the MOS transistor Q11 is off. Therefore, the MOS transistor Q1 is also turned off. In this state, no current flows through the previous stage MOS transistor Q.Q, and current also flows through the subsequent stage MOS transistor Q.Q of the inverter structure. No. In addition, Chitu 13
14 When the enable signal CE is at a high level "T", the MOS transistor Q16 is turned off, so the terminal N
The voltage V13 becomes the voltage 2 divided by the capacitors C and C2 of the second voltage setting section 2.

1 In other words, the voltage V13 is: ■=v=[C/<C+C2)]・Vcc132
11...(2) The voltage supply section 3, that is, the MOS transistor Q1
If the threshold voltage of transistor Q is vTE, then the voltage 15 PC2''-V=V-V...
(3) Output as PC2 2 7E. In this way, in this embodiment, during standby before operation of the memory cell array 52, no current flows through the MOS transistors Q11', Q12, Q13, and Q14, and a constant voltage V determined by the divided voltages of the capacitors C and C2 is maintained. PC2 can be applied to the memory cell array 52.

Next, when the chip enable signal CE is set to low level "L" to operate the memory cell array 52, the MOS transistor Q13 is turned on and the MOS transistor Q1 is turned off in the voltage setting section 1 of FIG. M.O.S.
When the transistor Q13 turns on, the MOS transistor Q11 also turns on, and the previous stage MOS transistor Q11. Current flows through Q12, and the subsequent stage MOS transistor Q
Current also flows through Q, and MOS transistors Q, QQ, and Q are connected to transistors 1112 and 1112 in FIG.
1314 operates in the same manner as the aforementioned MOS transistors Q, Q2122, Q23' and Q24. That is, terminal N
11 is set with a voltage V1 which is small enough to drive the memory cell array 52, and this voltage V1 is set to the MOS
In addition to the gate of the transistor Q14, a voltage V1 determined by the threshold voltage V of the MOS transistors 13 and 14 Q is applied to the terminal N12 by the MOS transistor QQ having an inverter configuration.
THLI V1 = ■CC 'TIIL1 ""
”(4).

When the chip enable signal CE is at the low level "L", the MOS transistor Q16 is also turned on, so the voltage V13 at the terminal N has the same value as the voltage V1 at the terminal N12, and the voltage supply section 3, that is, the MOS transistor
It is applied to the gate of the transistor Q15 and output as a predetermined voltage V 2 from the drain of the MQS transistor Q15, that is, the terminal N 2 . Su14
PC1, that is, the voltage ■ is PCI V=V-V ・・・・・・(5)P
It is output as C1 1 TE. In this way, the memory cell array 5
When operating MOS transistors QQQ,
Apply current to Q and set 11 = 12' 13
14 can be applied to the memory cell array 52PCI.

By the way, in this embodiment, by setting the capacitance ratio of the capacitors C and C2 of the second voltage setting section 2 to an appropriate value, the bias voltage V applied during standby is changed from the bias voltage V applied during the active state to the bias voltage V applied during the active state. can be set to the same value.

PCI For example, power supply voltage V at the gate. The capacitor C1 is composed of an n-channel enhancement type MOS transistor whose source and drain are connected to the terminal N13.
The capacitor C2 can be configured by diffusion junction capacitance, inter-wiring capacitance, and the like. In this case, by changing the gate oxide film thickness of the n-channel enhancement type MOS transistor with capacitor C1 on top, the mutual conductance glml of this MOS transistor is changed,
The capacitance of the capacitor C1 can be changed in the same direction as the direction in which the mutual conductance g1 increases or decreases. By adjusting the mutual conductance g in this way and making the bias voltage during standby the same as the bias voltage V during the active PC2 state, PCI can be achieved. 52 to make the enable access time the same as the address access time.

Also, by using the chip enable signal CE as a clock signal during standby, the bias voltage V,
becomes more stable. However, MOS transistor PCI PC2 transistor Q, QQ, Q active 11 1
2' 13 14 There is a need to shorten the period.

〔Effect of the invention〕

As explained above, according to the present invention, the first voltage setting means does not operate when the memory cell array is inactive, that is, during standby, and the bias voltage based on the divided voltage from the second voltage setting means is set. Since the voltage is supplied to the memory cell array, current consumption during standby can be significantly reduced, and an optimal bias voltage can always be generated and supplied to the memory cell array.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of a voltage generation circuit according to the present invention, and FIG. 2 is a configuration diagram of a conventional voltage generation circuit. DESCRIPTION OF SYMBOLS 1... First voltage setting section, 2... Second voltage setting section, 3... Voltage supply section, 5 2... Memory cell array

Claims (1)

[Claims] a first voltage setting means that does not operate when the memory cell array is not in operation and outputs a predetermined voltage when the memory cell array is in operation; and a second voltage setting means that outputs a divided predetermined voltage when the memory cell array is not in operation. When the memory cell array is not in operation, the voltage from the second voltage setting means is applied, and when the memory cell array is in operation, the voltage from the first voltage setting means is added to supply a predetermined bias voltage to the memory cell array. A voltage generating circuit comprising: supply means.