KR970013749A

KR970013749A - High voltage level detector

Info

Publication number: KR970013749A
Application number: KR1019950027272A
Authority: KR
Inventors: 김창현
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-08-29
Filing date: 1995-08-29
Publication date: 1997-03-29

Abstract

본 발명은 반도체 장치의 고전압 레벨 검출기에 관한 것으로서, 특히 노말모드에서는 저전위를 가지며, 퓨즈용단 모드에서는 고전위를 가지는 외부전원 전압신호가 인가되는 외부전원단자; 노말모드에서는 상기 외부전원 전압신호의 레벨보다 높고 퓨즈용단모드에서는 상기 외부전원 전압신호의 레벨보다 낮은 일정 전위를 가지는 제1내부전원 전압신호가 인가되는 제1내부전원단자; 제1노드와 접지단자 사이에 연결되고 상기 제1내부전원 전압신호에 응답하여 턴온되어 제1노드를 풀다운시키는 풀다운수단; 및 외부전원단자와 상기 제1노드 사이에 연결되고 상기 제1내부전원 전압신호에 응답하여 노말모드에서는 턴오프되고 퓨즈용단모드에서는 턴온되어 제1노드를 풀업시키는 풀업수단을 구비하는 것을 특징으로 한다. 따라서, 본 발명에서는 회로구성이 보다 간단하며 노말모드에서의 DC전력소모를 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage level detector of a semiconductor device, and in particular, an external power supply terminal having a low potential in a normal mode and an external power supply voltage signal having a high potential in a fuse short mode; A first internal power supply terminal to which a first internal power supply voltage signal having a predetermined potential higher than a level of the external power supply voltage signal in a normal mode and lower than a level of the external power supply voltage signal in a fuse short mode; Pull-down means connected between a first node and a ground terminal and turned on in response to the first internal power supply voltage signal to pull down the first node; And a pull-up means connected between an external power supply terminal and the first node and turned off in a normal mode in response to the first internal power supply voltage signal, and turned on in a fuse short mode to pull up the first node. . Therefore, in the present invention, the circuit configuration is simpler and DC power consumption in the normal mode can be prevented.

Description

High voltage level detector

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 고전압 레벨 검출기의 구성을 나타낸 블럭도.2 is a block diagram showing the configuration of a high voltage level detector according to the present invention.

제3도는 본 발명에 의한 고전압 레벨 검출기의 바람직한 일실시예의 회로도.3 is a circuit diagram of a preferred embodiment of a high voltage level detector according to the present invention.

Claims

An external power supply terminal having a low potential in the normal mode and an external power supply voltage signal having a high potential in the fuse short mode; A first internal power supply terminal to which a first internal power supply voltage signal having a predetermined potential higher than a level of the external power supply voltage signal in a normal mode and lower than a level of the external power supply voltage signal in a fuse short mode; Pull-down means connected between a first node and a ground terminal and turned on in response to the first internal power supply voltage signal to pull down the first node; And a pull-up means connected between an external power supply terminal and the first node and turned off in a normal mode in response to the first internal power supply voltage signal, and turned on in a fuse short mode to pull up the first node. High voltage level detector.

The high voltage level detector of claim 1, wherein the pull-up means comprises a PMOS transistor having a gate connected to a first internal power supply terminal, a drain connected to a first node, and a source and an engine connected to an external power supply terminal.

3. The high voltage level detector of claim 2, wherein the pull-down means comprises an NMOS transistor connected to a gate first internal power supply terminal, a drain connected to a first node, and a source connected to a ground terminal.

The semiconductor device of claim 1, wherein the pull-up means comprises: a first PMOS transistor having a gate connected to a first internal power supply terminal, a drain connected to a first node, a source connected to a second node, and a substrate connected to an external power supply terminal; And a second PMOS transistor having a gate and a drain connected to the second node, and a source and a substrate connected to an external power supply terminal.

The semiconductor device of claim 4, wherein the pull-down means comprises: a first NMOS transistor having a gate connected to a first internal power supply terminal, a drain connected to a first node, and a source connected to a third node; And a second NMOS transistor having a gate connected to the first internal power supply terminal, a drain connected to the third node, and a source connected to the ground terminal.

An external power supply terminal having a low potential in the normal mode and an external power supply voltage signal having a high potential in the fuse short mode; A first internal power supply terminal to which a first internal power supply voltage signal having a predetermined potential higher than a level of the external power supply voltage signal in a normal mode and lower than a level of the external power supply voltage signal in a fuse short mode; A second internal power supply terminal to which a second internal power supply voltage signal having a potential equal to the level of the external power supply voltage signal in the normal mode is applied; Pull-down means connected between a first node and a ground terminal and turned on in response to the second internal power supply voltage signal to pull down the first node; And a pull-up means connected between an external power supply terminal and the first node and turned off in a normal mode in response to the first internal power supply voltage signal, and turned on in a fuse short mode to pull up the first node. High voltage level detector.

※ Note: The disclosure is based on the initial application.