KR970024603A - Schmitt trigger circuit - Google Patents

Schmitt trigger circuit Download PDF

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Publication number
KR970024603A
KR970024603A KR1019950038740A KR19950038740A KR970024603A KR 970024603 A KR970024603 A KR 970024603A KR 1019950038740 A KR1019950038740 A KR 1019950038740A KR 19950038740 A KR19950038740 A KR 19950038740A KR 970024603 A KR970024603 A KR 970024603A
Authority
KR
South Korea
Prior art keywords
inverter
output terminal
schmitt trigger
trigger circuit
terminal
Prior art date
Application number
KR1019950038740A
Other languages
Korean (ko)
Other versions
KR0169416B1 (en
Inventor
이병준
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950038740A priority Critical patent/KR0169416B1/en
Publication of KR970024603A publication Critical patent/KR970024603A/en
Application granted granted Critical
Publication of KR0169416B1 publication Critical patent/KR0169416B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/013—Modifications of generator to prevent operation by noise or interference

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야 : 본 발명은 반도체 메모리 장치에 관한 것으로, 특히 슈미트 트리거 회로에 관한 것이다.1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a Schmitt trigger circuit.

2. 발명이 해결하려고 하는 기술적 과제 : 칩내에 차지하는 면적의 감소 및 고속동작을 수행할 수 있는 슈미트 트리거회로를 제공함에 있다.2. A technical problem to be solved by the present invention is to provide a Schmitt trigger circuit capable of reducing the area occupied in a chip and performing a high speed operation.

3. 발명의 해결방법의 요지 : 입려단자로 입력되는 신호를 반전시키기 위한 제1인버어터와, 상기 제1인버어터의 출력단자와 접속되어 상기 반전시킨 신호를 재차 반전시키기위한 제2인버어터와, 상기 제2인버어터의 출력단자와 상기 제1인버어터의 출력단자사이에 접속되어 상기 제2인버어터의 출력신호를 피드백시키기 위한 피드백회로를 구비한다.3. Summary of the Invention: A first inverter for inverting the signal input to the incoming terminal, a second inverter connected to the output terminal of the first inverter and inverting the inverted signal again; And a feedback circuit connected between the output terminal of the second inverter and the output terminal of the first inverter to feed back the output signal of the second inverter.

Description

슈미트 트리거 회로Schmitt trigger circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A,2B도는 본 발명에 따라 구성된 슈미트 트리거회로의 블럭도 및 기호,2A and 2B are block diagrams and symbols of Schmitt trigger circuits constructed in accordance with the present invention;

제3A,3B도는 본 발명에 따라 구성된 구체적인 슈미트 트리거회로도.3A and 3B are detailed Schmitt trigger circuit diagrams constructed in accordance with the present invention.

Claims (3)

슈미트 트리거회로에 있어서, 입력단자로 입력되는 신호를 반전시키기 위한 제1인버어터와, 상기 제1인버어터의 출력단자와 접속되어 상기 반전시킨 신호를 재차 반전시키기위한 제2인버어터와, 상기 제2인버어터의 출력단자와 상기 제1인버어터의 출력단자사이에 접속되어 상기 제2인버어터의 출력신호를 피드백시키기 위한 피드백 회로로 구성됨을 특징으로 하는 슈미트 트리거회로.A Schmitt trigger circuit comprising: a first inverter for inverting a signal input to an input terminal, a second inverter connected to an output terminal of the first inverter, for inverting the inverted signal again, and the first inverter And a feedback circuit connected between the output terminal of the second inverter and the output terminal of the first inverter to feed back the output signal of the second inverter. 제1항에 있어서, 상기 피드백회로는 상기 제2인버어터의 출력단자에 접속된 게이트와, 전원전압단자에 접속된 소오스와, 상기 제1인버어터의 출력단자에 접속된 드레인을 가지는 피모오스 프랜지스터임을 특징으로 하는 슈미트 트리거회로.The PMOS transistor of claim 1, wherein the feedback circuit has a gate connected to an output terminal of the second inverter, a source connected to a power supply voltage terminal, and a drain connected to an output terminal of the first inverter. Schmitt trigger circuit characterized in that it is a stur. 제1항에 있어서, 상기 피드백회로는 상기 제2인버어터의 출력단자에 접속된 게이트와, 접지전압단자에 접속된 소오스와, 상기 제1인버어터의 출력단자에 접속된 드레인을 가지는 엔모오스 프랜지스터임을 특징으로 하는 슈미트 트리거회로.The en-MOS flange of claim 1, wherein the feedback circuit has a gate connected to an output terminal of the second inverter, a source connected to a ground voltage terminal, and a drain connected to the output terminal of the first inverter. Schmitt trigger circuit characterized in that it is a stur. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950038740A 1995-10-31 1995-10-31 Schmitt-trigger circuit KR0169416B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950038740A KR0169416B1 (en) 1995-10-31 1995-10-31 Schmitt-trigger circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950038740A KR0169416B1 (en) 1995-10-31 1995-10-31 Schmitt-trigger circuit

Publications (2)

Publication Number Publication Date
KR970024603A true KR970024603A (en) 1997-05-30
KR0169416B1 KR0169416B1 (en) 1999-03-20

Family

ID=19432333

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950038740A KR0169416B1 (en) 1995-10-31 1995-10-31 Schmitt-trigger circuit

Country Status (1)

Country Link
KR (1) KR0169416B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429553B1 (en) * 2002-03-28 2004-05-03 주식회사 하이닉스반도체 Schmitt trigger circuit having constant hystersis in wide voltage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429553B1 (en) * 2002-03-28 2004-05-03 주식회사 하이닉스반도체 Schmitt trigger circuit having constant hystersis in wide voltage

Also Published As

Publication number Publication date
KR0169416B1 (en) 1999-03-20

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