KR970024588A - Reference Input Circuit of Semiconductor Memory Device - Google Patents

Reference Input Circuit of Semiconductor Memory Device Download PDF

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Publication number
KR970024588A
KR970024588A KR1019950034941A KR19950034941A KR970024588A KR 970024588 A KR970024588 A KR 970024588A KR 1019950034941 A KR1019950034941 A KR 1019950034941A KR 19950034941 A KR19950034941 A KR 19950034941A KR 970024588 A KR970024588 A KR 970024588A
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KR
South Korea
Prior art keywords
field effect
effect transistor
source
output terminal
gate
Prior art date
Application number
KR1019950034941A
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Korean (ko)
Inventor
임정주
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950034941A priority Critical patent/KR970024588A/en
Publication of KR970024588A publication Critical patent/KR970024588A/en

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Abstract

본 발명은 설계효율을 향상시키는 반도체 메모리 장치의 기준입력회로에 관해 게시한다. 종래에는 롬의 데이타를 독출하기 위하여 어드레스를 조합하여 독출했으나 본 발명은 감응증폭기와 기준입력회로를 이용하고 있다. 따라서 룸설계 효율이 향상된다. 본 발명의 구성은 2개의 입력을 갖는 낸드(NAND) 게이트와, 상기 낸드게이트의 출력단에 접속된 버퍼회로와, 상기 버퍼회로의 출력단에 게이트가 접속되고 전윈단자에 드레인이 접속된 제1전계효과 트랜지스터와 상기 버퍼회로의 출력단에 게이트가 접속되고 소오스가 접지단자에 접속된 제2전계효과 트랜지스터와 상기 제1전계효과 트랜지스터의 소오스에 드레인이 접속되고 게이트와 소오스가 접속된 제3전계효과 트랜지스터 및 상기 제3전계효과 트랜지스터의 소오스에 접속된 제1전계효과 트랜지스터의 소오스에 접속된 기준(reference) 출력단자로 구성한다.The present invention discloses a reference input circuit of a semiconductor memory device for improving design efficiency. Conventionally, in order to read ROM data, a combination of addresses are read, but the present invention uses a sensitive amplifier and a reference input circuit. Therefore, room design efficiency is improved. The structure of the present invention includes a NAND gate having two inputs, a buffer circuit connected to an output terminal of the NAND gate, and a first field effect in which a gate is connected to an output terminal of the buffer circuit and a drain is connected to an electric power terminal. A second field effect transistor having a gate connected to an output terminal of the transistor and the buffer circuit and a source connected to a ground terminal, and a third field effect transistor having a drain connected to a source of the first field effect transistor and a gate connected to the source; And a reference output terminal connected to the source of the first field effect transistor connected to the source of the third field effect transistor.

Description

반도체 메모리 장치의 기준입력회로Reference Input Circuit of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의한 반도체 메모리 장치의 기준입력회로.1 is a reference input circuit of a semiconductor memory device according to the present invention.

Claims (3)

2개의 입력을 갖는 낸드(NAND) 게이트; 상기 낸드게이트의 출력단에 접속된 버퍼회로; 상기 버퍼회로의 출력단에 게이트가 접속되고 전원단자에 드레인이 접속된 제1전계효과 트랜지스터; 상기 버퍼회로의 출력단에 게이트가 접속되고 소오스가 접지단자에 접속된 제2전계효과 트랜지스터; 상기 제1전계효과 트랜지스터의 소오스에 드레인이 접속되고 게이트와 소오스가 접속된 제3전계효과 트랜지스터; 및 상기 제3전계효과 트랜지스터의 소오스에 접속된 제1전계효과 트랜지스터의 소오스에 접속된 기준(reference) 출력단자를 포함하는 것을 특징으로 하는 반도체 메모리 장치의 기준입력회로.A NAND gate having two inputs; A buffer circuit connected to an output terminal of the NAND gate; A first field effect transistor having a gate connected to an output terminal of the buffer circuit and a drain connected to a power supply terminal; A second field effect transistor having a gate connected to an output terminal of the buffer circuit and a source connected to a ground terminal; A third field effect transistor having a drain connected to the source of the first field effect transistor and a gate connected to the source; And a reference output terminal connected to a source of the first field effect transistor connected to a source of the third field effect transistor. 제1항에 있어서, 상기 제1전계효과 트랜지스터와 제3전계효과 트랜지스터는 PMOS 트랜지스터인 것을 특징으로 하는 반도체 메모리 장치의 기준입력회로.The reference input circuit of claim 1, wherein the first field effect transistor and the third field effect transistor are PMOS transistors. 제1항에 있어서, 상기 제2전계효과 트랜지스터는 NMOS 트랜지스터인 것을 특징으로 하는 반도체 메모리 장치의 기준입력회로.The reference input circuit of claim 1, wherein the second field effect transistor is an NMOS transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950034941A 1995-10-11 1995-10-11 Reference Input Circuit of Semiconductor Memory Device KR970024588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950034941A KR970024588A (en) 1995-10-11 1995-10-11 Reference Input Circuit of Semiconductor Memory Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950034941A KR970024588A (en) 1995-10-11 1995-10-11 Reference Input Circuit of Semiconductor Memory Device

Publications (1)

Publication Number Publication Date
KR970024588A true KR970024588A (en) 1997-05-30

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ID=66583649

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950034941A KR970024588A (en) 1995-10-11 1995-10-11 Reference Input Circuit of Semiconductor Memory Device

Country Status (1)

Country Link
KR (1) KR970024588A (en)

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