KR970017673A - Method for generating virtual ground voltage of semiconductor memory device and its circuit - Google Patents

Method for generating virtual ground voltage of semiconductor memory device and its circuit Download PDF

Info

Publication number
KR970017673A
KR970017673A KR1019950030335A KR19950030335A KR970017673A KR 970017673 A KR970017673 A KR 970017673A KR 1019950030335 A KR1019950030335 A KR 1019950030335A KR 19950030335 A KR19950030335 A KR 19950030335A KR 970017673 A KR970017673 A KR 970017673A
Authority
KR
South Korea
Prior art keywords
voltage
transistor
terminal
ground
circuit
Prior art date
Application number
KR1019950030335A
Other languages
Korean (ko)
Other versions
KR0172335B1 (en
Inventor
박종민
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950030335A priority Critical patent/KR0172335B1/en
Publication of KR970017673A publication Critical patent/KR970017673A/en
Application granted granted Critical
Publication of KR0172335B1 publication Critical patent/KR0172335B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Electrical Variables (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

가상접지전압 생성회로.Virtual ground voltage generation circuit.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

하나의 단자를 가상접지 단자로서 사용하여 접지 전압을 인가하는 반도체 장치에 있어서 상기 접지단자에 상기 접지전압에 보다 가까운 전압을 인가할 수 있도록 함으로써, 상기 접지전압을 인가하는 일련의 동작이 원활히 수행하도록 하는데 있다.In a semiconductor device that applies a ground voltage by using one terminal as a virtual ground terminal, a voltage closer to the ground voltage can be applied to the ground terminal, so that a series of operations for applying the ground voltage can be performed smoothly. It is.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

내부에 고전압 발생회로가 존재하고, 상기 고전압 발생회로에 의해 고전압이 인가되는 단자를 동작 형태에 따라 접지 전위로도 사용하는 반도체 메모리 장치에 있어서, 상기 접지 전위는 두개의 트랜지스터에 의해 구성되며, 제1트랜지스터의 소오스 단자와 제2트랜지스터의 드레인 단자를 접속하고, 제2트랜지스터의 소오스 단자에 접지 전압을 인가한 후, 제1트랜지스터의 드레인 단자를 상기 접지 전위를 인가하고자 할 때, 상기 두개의 트랜지스터의 게이트에 전원 전압 이상의 전압을 인가하는 상기 접지 전위를 구성하는 것을 특징으로 한다.In a semiconductor memory device having a high voltage generation circuit therein and using a terminal to which a high voltage is applied by the high voltage generation circuit as a ground potential according to an operation type, the ground potential is formed by two transistors. When the source terminal of the first transistor and the drain terminal of the second transistor are connected, the ground voltage is applied to the source terminal of the second transistor, and when the drain terminal of the first transistor is intended to apply the ground potential, the two transistors The ground potential for applying a voltage equal to or greater than the power supply voltage to the gate is characterized in that the configuration.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 메모리에 사용된다.Used for semiconductor memory.

Description

반도체 메모리 장치의 가상접지전압 생성방법 및 그 회로Method for generating virtual ground voltage of semiconductor memory device and its circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 가상접지전압의 생성 회로도,3 is a circuit diagram for generating a virtual ground voltage according to the present invention;

제4도는 제3도중 고전압 발생회로의 세부 회로도.4 is a detailed circuit diagram of a high voltage generation circuit in FIG.

Claims (5)

칩 내부에 고전압 발생회로가 존재하고, 상기 고전압 발생회로에 의해 고전압이 인가되는 단자를 동작 형태에 따라 접지 전위로도 사용하는 반도체 메모리 장치에 있어서, 상기 접지 전위는 두개의 트랜지스터에 의해 설정되며, 제1트랜지스터의 소오스 단자와 제2트랜지스터의 드레인 단자를 접속하고, 제2트랜지스틴의 소오스 단자에 접지 전압을 인가간 후, 상기 제1트랜지스터의 드레인 단자에 상기 접지 전위를 인가하고자 할 때, 상기 두개의 트랜지스터의 게이트에 전원 전압 이상의 전압을 인가하여 상기 접지 전위를 생성하는 것을 특징으로 하는 회로.In a semiconductor memory device in which a high voltage generation circuit exists inside a chip, and a terminal to which a high voltage is applied by the high voltage generation circuit is also used as a ground potential according to an operation type, the ground potential is set by two transistors, When the source terminal of the first transistor is connected to the drain terminal of the second transistor, the ground voltage is applied to the source terminal of the second transistor, and when the ground potential is to be applied to the drain terminal of the first transistor. And generating a ground potential by applying a voltage higher than a power supply voltage to the gates of the two transistors. 제1항에 있어서, 상기 고전압 발생회로의 갯수는 상기 트랜지스터의 갯수와 동일함을 특징으로 하는 회로.The circuit of claim 1, wherein the number of the high voltage generating circuits is equal to the number of the transistors. 제2항에 있어서, 전원 전압 이상의 전압은 상기 전원 전압보다 1V-5V 높은 것을 특징으로 하는 회로.The circuit according to claim 2, wherein a voltage equal to or greater than the power supply voltage is 1V-5V higher than the power supply voltage. 엔형 디플리션 모오스 트랜지스터와 엔형 인핸스먼트 모오스 트랜지스터를 직렬로 접수하고 상기 엔형 인핸스먼트 트랜지스터의 소오스단자에 접지전압을 인가하고, 상기 접지 전압을 상기 엔형 디플리션 트랜지스터의 드레인단자에 전달하도록 하는 반도체 메모리의 가상 접지 전압 생성회로에 있어서, 상기 모오스 트랜지스터들의 각 게이트 단자에 출력단이 각기 연결되고, 제1,2전압신호에 각기 응답하여 상기 출력단에 고전압을 각기 인가하기 위한 제1,2고전압 발생회로를 가짐을 특징으로 하는 회로.A semiconductor for receiving an N type depletion mode transistor and an N type enhancement mode transistor in series, applying a ground voltage to a source terminal of the N type enhancement transistor, and transmitting the ground voltage to a drain terminal of the N type depletion transistor. In the virtual ground voltage generation circuit of the memory, an output terminal is connected to each gate terminal of the MOS transistors, respectively, the first and second high voltage generating circuit for applying a high voltage to the output terminal in response to the first and second voltage signals, respectively Circuit characterized in that it has a. 제4항에 있어서, 상기 제1,2전압신호는 전원 전압 및 펄스형태의 전압임을 특징으로 하는 회로.The circuit of claim 4, wherein the first and second voltage signals are a power supply voltage and a pulse voltage. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950030335A 1995-09-16 1995-09-16 Method of generating virtual ground voltage of semiconductor memory equipment and the circuit thereof KR0172335B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950030335A KR0172335B1 (en) 1995-09-16 1995-09-16 Method of generating virtual ground voltage of semiconductor memory equipment and the circuit thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950030335A KR0172335B1 (en) 1995-09-16 1995-09-16 Method of generating virtual ground voltage of semiconductor memory equipment and the circuit thereof

Publications (2)

Publication Number Publication Date
KR970017673A true KR970017673A (en) 1997-04-30
KR0172335B1 KR0172335B1 (en) 1999-03-30

Family

ID=19427012

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950030335A KR0172335B1 (en) 1995-09-16 1995-09-16 Method of generating virtual ground voltage of semiconductor memory equipment and the circuit thereof

Country Status (1)

Country Link
KR (1) KR0172335B1 (en)

Also Published As

Publication number Publication date
KR0172335B1 (en) 1999-03-30

Similar Documents

Publication Publication Date Title
KR870002653A (en) Complementary semiconductor device reduces latch spill
KR970013732A (en) Data output buffer using multi power
KR970029739A (en) Semiconductor potential supply device and semiconductor memory device using same
KR960030395A (en) Low-voltage output circuit and semiconductor device
KR970017673A (en) Method for generating virtual ground voltage of semiconductor memory device and its circuit
KR960019978A (en) Pulse generator
KR970017589A (en) Internal power supply voltage generation circuit of semiconductor memory device
KR960042746A (en) Dynamic Level Converters in Semiconductor Memory Devices
KR970051161A (en) Word line drive
KR970024603A (en) Schmitt trigger circuit
KR910015862A (en) Substrate Bias Voltage Detection Circuit
KR970003193A (en) Voltage generator circuit for external power supply voltage level detector
KR960042747A (en) Word Line Control Circuit of Semiconductor Memory
KR930005370A (en) Input circuit
KR970051078A (en) External Input Signal Detection Circuit in Semiconductor Memory Device
KR970003213A (en) Data output buffer
KR980004936A (en) Internal Voltage Generator for Semiconductor Memory Devices
KR940026957A (en) High voltage transmission circuit
KR960002802A (en) Semiconductor device with high speed input circuit
KR970024585A (en) BSI MOOS Logic Circuit
KR910005311A (en) Polar programmable enable circuit
KR970078009A (en) The input buffer of the semiconductor memory device
KR970013735A (en) Output buffer circuit
KR970008865A (en) Short pulse generator with preset function
KR970051102A (en) High voltage generator

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050909

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee