KR970003193A - Voltage generator circuit for external power supply voltage level detector - Google Patents

Voltage generator circuit for external power supply voltage level detector Download PDF

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Publication number
KR970003193A
KR970003193A KR1019950018290A KR19950018290A KR970003193A KR 970003193 A KR970003193 A KR 970003193A KR 1019950018290 A KR1019950018290 A KR 1019950018290A KR 19950018290 A KR19950018290 A KR 19950018290A KR 970003193 A KR970003193 A KR 970003193A
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South Korea
Prior art keywords
power supply
supply voltage
mos transistor
reference voltage
voltage
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KR1019950018290A
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Korean (ko)
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KR0158486B1 (en
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김창현
남가표
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김광호
삼성전자 주식회사
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Priority to KR1019950018290A priority Critical patent/KR0158486B1/en
Publication of KR970003193A publication Critical patent/KR970003193A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Electrical Variables (AREA)
  • Dram (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 외부 전원 전압 레벨 감지기에서의 기준 전압 발생 회로에 관한 반도체 메모리 분야이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor memories relating to reference voltage generator circuits in external power supply voltage level detectors.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

본 발명은 여러 내부회로들에 구비되는 외부 전원 전압 레벨 감지기에서의 기준 전압 발생기에서 그것을 구성하는 두개의 모오스트랜지스터중 하나의 게이트입력을 내부회로들마다 다른 일정전압으로 인가하여 게이트입력된 모오스 트랜지스터의 전류량을 일정하게 만들어 줌으로써 유효 저항을 더욱 증가시켜 외부 전원 전압의 변화에 비례해서 소정 레벨의 기준 전압을 변화시키는 기준 전압 발생 회로를 제공한다.The present invention provides a gate input of a MOS transistor gated by applying a gate input of one of two MOS transistors constituting it in a reference voltage generator in an external power supply voltage level detector provided in various internal circuits with a different constant voltage for each internal circuit. By providing a constant current amount, an effective resistance is further increased to provide a reference voltage generating circuit that changes a reference voltage at a predetermined level in proportion to a change in an external power supply voltage.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명은 달성하기 위하여 본 발명은 외부 전원 전압 레벨 감지기에서 제1 및 제2전원전압의 레벨에 따라 소정 레벨의 전압을 공급하는 기준 전압 발생 회로에 있어서, 제1전원전압단자에 일측이 접속되고 제2전원전압단자에 게이트가 접속된 제1모오스 트랜지스터와, 게이트에 일정전압이 인가되고 상기 제1모오스 트랜지스터의 일측과 접속되고 상기 제2전원전압단자에 타측이 접속되는 제2모오스 트랜지스터와, 상기 제1모오스 트랜지스터와 상기 제2모오스 트랜지스터가 접속된 노드와 접속되어 소정 레벨의 전압을 공급하는 출력단자로 구성하는 기준 전압 발생 회로를 특징으로 한다.In order to achieve the present invention, the present invention provides a reference voltage generating circuit for supplying a predetermined level of voltage according to the level of the first and second power supply voltages in an external power supply voltage level detector, wherein one side is connected to the first power supply voltage terminal. A first MOS transistor having a gate connected to a second power supply voltage terminal, a second MOS transistor having a constant voltage applied to the gate, connected to one side of the first MOS transistor, and connected to the second power supply voltage terminal at the other side thereof; And a reference voltage generator circuit configured as an output terminal for supplying a voltage of a predetermined level by being connected to a node to which the first MOS transistor and the second MOS transistor are connected.

4. 발명의 중요한 용도4. Important uses of the invention

외부 전원 전압 레벨 감지기를 구비하는 반도체 메모리장치에 사용된다.It is used in a semiconductor memory device having an external power supply voltage level detector.

Description

외부 전원 전압 레벨 감지기에서의 기준 전압 발생 회로Voltage generator circuit for external power supply voltage level detector

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도는 본 발명에 따른 일실시예로서의 기준 전압 발생 회로의 회로도.2A is a circuit diagram of a reference voltage generator circuit as one embodiment according to the present invention.

Claims (6)

외부 전원 전압 레벨 감지기에 제1 및 제2전원전압의 레벨에 따라 소정 레벨의 전압을 공급하는 기준 전압 발생 회로에 있어서,제1전원전압단자에 일측이 접속되고 제2전원전압단자에 게이트가 접속된 제1모오스 트랜지스터와, 게이트에 일정전압이 인가되고 상기 제1모오스 트랜지스터의 일측과 접속되고 상기 제2전원전압단자에 타측이 접속되는 제2모오스 트랜지스터와, 상기 제1모오스 트랜지스터와 상기 제2모오스 트랜지스터가 접속된 노드와 접속되어 소정 레벨의 전압을 공급하는 출력단자로 구성함을 특징으로 하는 기준 전압 발생 회로.In a reference voltage generator circuit for supplying a voltage of a predetermined level to an external power supply voltage level detector according to a level of first and second power supply voltages, one side is connected to a first power supply voltage terminal and a gate is connected to a second power supply voltage terminal. The first MOS transistor, a second voltage transistor having a constant voltage applied to a gate thereof, connected to one side of the first MOS transistor, and the other side connected to the second power supply voltage terminal, the first MOS transistor, and the second A reference voltage generator circuit comprising an output terminal for supplying a predetermined level of voltage connected to a node to which a MOS transistor is connected. 제1항에 있어서, 상기 제1모오스 트랜지스터와 상기 제2모오스 트랜지스터는 각각 피모오스 트랜지스터, 앤모오스 트랜지스터임을 특징으로 하는 기준 전압 발생 회로.The reference voltage generator of claim 1, wherein the first and second MOS transistors are PMOS transistors and NMOS transistors, respectively. 제1항에 있어서, 상기 제1모오스 트랜지스터와 상기 제2모오스 트랜지스터는 앤모오스 트랜지스터임을 특징으로 하는 기준 전압 발생 회로.The reference voltage generator of claim 1, wherein the first and second MOS transistors are NMOS transistors. 외부 전원 전압 레벨 감지기에 제1 및 제2전원전압의 레벨에 따라 소정 레벨의 전압을 공급하는 기준전압 발생 회로에 있어서, 게이트에 일정전압이 인가되고 제1전원전압단자에 일측이 접속되는 제1모오스 트랜지스터와, 상기 제1모오스 트랜지스터의 일측과 접속되고 상기 제2전원전압단자에 타측이 접속되고 게이트에 제1전원전압단자가 접속되는 제2모오스 트랜지스터와, 상기 제1모오스 트랜지스터와 상기 제2모오스 트랜지스터가 접속된 노드와 접속되어 소정 레벨의 전압을 공급하는 출력단자로 구성함을 특징으로 하는 기준 전압 발생 회로.In a reference voltage generation circuit for supplying a voltage of a predetermined level to the external power supply voltage level detector according to the level of the first and second power supply voltages, a first voltage is applied to a gate and one side is connected to the first power supply voltage terminal. A MOS transistor, a second MOS transistor connected to one side of the first MOS transistor, the other side connected to the second power supply voltage terminal, and a first power supply voltage terminal connected to a gate, the first MOS transistor, and the second A reference voltage generator circuit comprising an output terminal for supplying a predetermined level of voltage connected to a node to which a MOS transistor is connected. 제4항에 있어서, 상기 제1모오스 트랜지스터와 상기 제2모오스 트랜지스터는 각각 피모오스 트랜지스터, 엔모오스 트랜지스터임을 특징으로 하는 기준 전압 발생 회로.The reference voltage generator of claim 4, wherein the first and second MOS transistors are PMOS transistors and NMOS transistors, respectively. 제4항에 있어서, 상기 제1모오스 트랜지스터와 상기 제2모오스 트랜지스터는 모두 엔모오스 트랜지스터임을 특징으로 하는 기준 전압 발생 회로.The reference voltage generator of claim 4, wherein both of the first and second MOS transistors are NMOS transistors. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950018290A 1995-06-29 1995-06-29 Reference voltage generator circuit KR0158486B1 (en)

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KR1019950018290A KR0158486B1 (en) 1995-06-29 1995-06-29 Reference voltage generator circuit

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100432345B1 (en) * 2001-08-31 2004-05-20 삼성전자주식회사 Signal receiver apparatus and method for detecting logic state represented by an input signal and semiconductor integrated circuit device having the same
KR100471143B1 (en) * 1997-12-31 2005-06-07 삼성전자주식회사 Reference voltage generating circuit of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100471143B1 (en) * 1997-12-31 2005-06-07 삼성전자주식회사 Reference voltage generating circuit of semiconductor device
KR100432345B1 (en) * 2001-08-31 2004-05-20 삼성전자주식회사 Signal receiver apparatus and method for detecting logic state represented by an input signal and semiconductor integrated circuit device having the same

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