KR970011653B1 - Formation method of contact hole measurement mark - Google Patents

Formation method of contact hole measurement mark Download PDF

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Publication number
KR970011653B1
KR970011653B1 KR1019940001947A KR19940001947A KR970011653B1 KR 970011653 B1 KR970011653 B1 KR 970011653B1 KR 1019940001947 A KR1019940001947 A KR 1019940001947A KR 19940001947 A KR19940001947 A KR 19940001947A KR 970011653 B1 KR970011653 B1 KR 970011653B1
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South Korea
Prior art keywords
contact hole
layer
measurement mark
forming
cell
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KR1019940001947A
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Korean (ko)
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KR950025942A (en
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함영목
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현대전자산업 주식회사
김주용
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Priority to KR1019940001947A priority Critical patent/KR970011653B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Memories (AREA)

Abstract

Measurement mark forming method selects the layer to be contacted on the upper part of semiconductor substrate and forms the surface with diffusion layer(1), the first polycrystalline silicon layer(3), the second polycrystalline silicon layer(5), and the third polycrystalline silicon layer(7), and then applies insulation film on the upper part. Next, whenever the process is in progress, the measurement mark is formed by defining on the each layer as stepping up one step at a time and forming contact hole that is to be analyzed.

Description

콘택홀(contact hole) 측정용 측정마크 형성방법Method of forming a measuring mark for measuring contact holes

제1도는 본 발명의 실시예에 의한 콘택홀 측정용 측정마크를 도시한 단면도.1 is a cross-sectional view showing a measurement mark for measuring a contact hole according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 확선층(diffusion layer),2, 4, 6, 8 : 콘택홀,1: diffusion layer, 2, 4, 6, 8: contact hole,

3 : 제1다결정실리콘층,5 : 제2다결정실리콘층,3: first polycrystalline silicon layer, 5: second polycrystalline silicon layer,

7 : 제3다결정실리콘층,10 : 절연막,7: third polycrystalline silicon layer, 10: insulating film,

20 : 반도체 기판20: semiconductor substrate

본 발명은 콘택홀 측정용 측정마크 형성방법에 관한 것으로, 스크라이브라인 계단형으로 셀부분에 형성될 층을 미리 형성한 다음, 그 상부에 절연막을 도포하고 셀부분에 예정된 공정에 의해 콘택홀을 형성할 때 상기 스크라이브라인에 같은 콘택홀을 형성하여 측정마크를 형성하며 반복되는 구조는 한 가지만을 형성한 것이다. 상기 측정마크는 각층의 특성에 맞추어 공정을 진행하여 셀부의 특성을 파악할 수 있으며 DRAM이나 SRAM에 실제 적용될 수 있는 기술이다.The present invention relates to a method for forming a measurement mark for measuring a contact hole, wherein a layer to be formed in a cell portion is formed in advance in a scribe brine step, and then an insulating film is coated on the upper portion thereof to form a contact hole by a predetermined process in the cell portion. When forming the same contact hole in the scribe brine to form a measurement mark and the repeated structure is formed of only one. The measurement mark is a technology that can determine the characteristics of the cell portion by proceeding the process according to the characteristics of each layer and can be actually applied to DRAM or SRAM.

디램셀 제조시 설계된대로 진행되는지를 알기 위하여 콘택홀의 선폭을 측정하는 것은 필수적이며, 일반적으로 콘택홀의 선폭측정은 각각의 층를 공정할 때 분석하기 때문에 임의의 층을 형성할 때 다른 층의 콘택홀의 선폭은 알 수가 없다. 그래서, 각각의 층에 대해서 모두를 측정하여 하는 공정이 필요한데 많은 시간이 소비되며 많은 측정공정을 필요로 한다. 따라서, 상기 디램셀이 4M(mega)라고 할 때 한개의 셀당 한개의 콘택홀이 형성된다고 하면 4×106개 만큼 콘택홀이 형성되어 시간적 손실이 크고 많은 측정공정을 실시함으로써 오차가 발생할 수 있는 문제점이 대두되었다.It is essential to measure the line width of the contact hole to know if it proceeds as designed when manufacturing the DRAM cell. In general, the line width of the contact hole is analyzed during processing of each layer. Is unknown. Therefore, a process that measures all of each layer is required, which takes a lot of time and requires a lot of measuring processes. Therefore, when the DRAM cell is 4M (mega), if one contact hole is formed per cell, as many as 4 × 10 6 contact holes are formed, and time loss is large, and error may occur by performing a large number of measurement processes. Problems have arisen.

따라서, 본 발명은 셀의 제조공정시 실험 및 분석을 위하여 찾기쉬운 일정부위에 셀부위와 같은 단차의 갖는 층을 적층하되 계단형으로 형성하고 셀부위에 콘택홀을 형성할 때 상기 일정부위에서 같은 층을 형성하는 층에 같은 콘택홀을 형성하여 측정마크로 사용하는 것을 그 목적으로 한다.Therefore, the present invention is to stack the layer having the same step as the cell site on the predetermined site for the experiment and analysis during the manufacturing process of the cell, but to form a stepped and to form a contact hole in the cell site at the same site It is an object to form the same contact hole in the layer forming the layer and to use it as a measurement mark.

이상의 목적을 달성하기 위한 본 발명의 특징은, 실험 및 분석을 위하여 찾기 쉬운 일정부위에 셀에 형성될 각각의 층을 계단형으로 미리 적층한 후, 절연막을 전체구조상부에 도포하는 공정과, 셀부분에 콘택홀을 형성할 때 상기 콘택홀을 형성하는 부분과 단차가 같은 상기 일정부위의 각층에 콘택홀을 형성하는 공정을 포함하는데 있다.A feature of the present invention for achieving the above object is a step of preliminarily laminating each layer to be formed in a cell on a predetermined portion for easy experiment and analysis, and then applying an insulating film on the entire structure, and And forming a contact hole in each layer of the predetermined portion having the same step as the portion for forming the contact hole when forming the contact hole in the portion.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1도는 본 발명에 의한 콘택홀 측정용 측정마크를 도시한 단면도이다.1 is a cross-sectional view showing a measurement mark for measuring a contact hole according to the present invention.

제1도는 반도체기판(20) 상부에 미리 콘택될 층을 선택하여 확산층(diffusion layer)(1), 제1다결정실리콘층(3), 제2다결정실리콘층(5) 및 제3다결정실리콘층(7)을 각각 중첩되게 형성하고 그 상부에 절연막(10)을 도포한 다음, 공정이 진행될 때마다 단차가 한 단계씩 올라가며 분석하고자 하는 콘택홀 형성시 각각의 층에 디파인(define)하여 측정마크를 형성한 것을 도시한 단면도이다. 여기서, 상기 각층간의 단차에 형성된 콘택홀(2, 4, 6, 8)은 실제 제품에서의 콘택홀은 상기 측정마크와 같은 구조로 형성되기 때문에 본 발명에 의한 측정마크를 측정함으로써 소자의 특성을 알 수 있다. 그리고, 상기 측정마크는 소자의 스크라이브라인(scribe line) 지역 또는 소자의 한쪽 구석과 같이 잘보이는 빈 공간에 형성하며, x축방향으로 3개 이상을 형성하고 y축방향으로 3개 이상을 형성하는 것이 보통이다. 또한, 상기 측정마크는 셀에 형성되는 많은 유형중에서 각 유형별로 한가지씩을 형성한 것으로써, 종래와 달리 임의의 어떤 층을 측정할 때 다른 층을 측정할 수도 있다.FIG. 1 shows a diffusion layer 1, a first polysilicon layer 3, a second polysilicon layer 5 and a third polysilicon layer by selecting a layer to be contacted in advance on the semiconductor substrate 20. 7) are formed to overlap each other, and the insulating film 10 is applied on the upper part thereof, and each step progresses, the step increases by one step, and when the contact hole to be analyzed is formed, it is defined in each layer to define the measurement mark. It is sectional drawing which shows what was formed. Here, the contact holes (2, 4, 6, 8) formed in the step between each layer is a contact hole in the actual product is formed in the same structure as the measurement mark, the characteristics of the device by measuring the measurement mark according to the present invention Able to know. In addition, the measurement mark is formed in a scribe line region of the device or an empty space that is easily seen as one corner of the device, and forms three or more in the x-axis direction and three or more in the y-axis direction. Is common. In addition, the measurement mark is formed of one of each type among the many types formed in the cell, unlike the conventional one may measure another layer when measuring any one layer.

상기한 본 발명에 의하면, 단차에 의한 각층의 특성에 따른 콘택홀의 특성을 알 수 있으며 실제 공정에 적용함으로써, 각층에 콘택홀을 형성할 때마다 측정하여야 하는 불편함을 해소하며 DRAM이나 SRAM 등의 4소자에 적용가능하다.According to the present invention, it is possible to know the characteristics of the contact hole according to the characteristics of each layer due to the step, and by applying to the actual process, to eliminate the inconvenience to be measured every time the contact hole is formed in each layer, such as DRAM or SRAM Applicable to four elements.

Claims (2)

콘택홀 측정용 측정마크 형성방법에 있어서, 실험 및 분석을 위하여 찾기 쉬운 일정부위에 셀에 형성될 각각의 층을 계단형으로 미리 적층한 후, 절연막을 전체구조상부에 도포하는 공정과, 셀부분에 콘택홀을 형성할 때 상기 콘택홀을 형성하는 부분과 단차가 같은 상기 일정부위의 각층에 콘택홀을 형성하는 공정을 특징으로 하는 콘택홀 측정용 측정마크 형성방법.In the method of forming a measurement mark for measuring contact holes, a step of preliminarily laminating each layer to be formed in a cell on a predetermined portion for easy experiment and analysis, and then applying an insulating film on the entire structure, and a cell portion. Forming a contact hole in each layer of the predetermined portion having the same level as the step forming the contact hole when forming the contact hole in the contact hole; 제1항에 있어서, 상기 측정마크는 찾기 쉬운 셀의 구석이나 스크라이브라인에 형성하는 것을 특징으로 하는 콘택홀 측정용 측정마크 형성방법.The method of claim 1, wherein the measurement mark is formed at a corner or scribe brine of a cell that is easy to find.
KR1019940001947A 1994-02-03 1994-02-03 Formation method of contact hole measurement mark KR970011653B1 (en)

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KR970011653B1 true KR970011653B1 (en) 1997-07-12

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